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1
Trenz Electronic FPGA Modules / Re: TE0820 reference design vivado 2022.2
« Last post by JH on February 08, 2023, 01:36:54 PM »
Hi,
yes, but I can't tell any timeline at the moment.
You can start with 21.2 and update simple to 22.2 if this works depends on AMD(Xilinx) changes between these vivado versions.
br
John
2
Trenz Electronic FPGA Modules / TE0820 reference design vivado 2022.2
« Last post by kraster on February 08, 2023, 09:39:33 AM »
have you already planned a 2022.2 release?

thanks
3
Trenz Electronic FPGA Modules / Re: TE0720 LED1 and LED2
« Last post by JH on February 06, 2023, 08:09:48 AM »
Hi,
did you update CPLD to the newest firmware? I think you has a older one. Firmware documentation and new firmware release was  around June last year, see:
https://wiki.trenz-electronic.de/display/PD/TE0720+CPLD#TE0720CPLD-DocumentChangeHistory


PS:
Quote
Also, I have asked this before, but does anyone know what device 0x21 is on I2C bus 1?
Are you sure that nobody answered?
https://forum.trenz-electronic.de/index.php/topic,1715.msg8128.html#msg8128
On older CPLD Version other I2C end device IP was used and 2 addresses was available, see a older obsolete documentation:
https://wiki.trenz-electronic.de/display/PD/TE0720+CPLD+archive+obsolete+description

br
John
4
Trenz Electronic FPGA Modules / Re: TE-0720 unique serial number
« Last post by JH on February 06, 2023, 08:02:58 AM »
Hi,
yes and no....but that's more a AMD internal question, you should write to AMD support(community is much bigger there) and check Zynq documentation, in case you has SoC internal questions.
See also: https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html#documentation
br
John
5
Trenz Electronic FPGA Modules / Re: TE0720 custom carrier - Petalinux (2020.2) issues
« Last post by JH on February 06, 2023, 06:42:44 AM »
Hi,
I think this was some bug from 20.2 version. AMD change style more and more to yocto...and some version  are not completely implemented.
Here are some notes what we found out on this version
https://wiki.trenz-electronic.de/display/PD/Petalinux+Troubleshoot#PetalinuxTroubleshoot-Petalinux2020.2

br
John
6
Trenz Electronic FPGA Modules / Re: connect TE0820 JTAG with a JTAG verilog design
« Last post by JH on February 06, 2023, 06:39:49 AM »
Hi,
yes it's possible.either you use Xilinx axi master (you can controll IP over Vivado TCL command shell) or Xilinx VIO Core:
https://www.xilinx.com/products/intellectual-property/jtag_to_axi_master.html
https://www.xilinx.com/products/intellectual-property/vio.html

You can also get direclty access to JTAG:
https://docs.xilinx.com/r/en-US/ug974-vivado-ultrascale-libraries/MASTER_JTAG
br
John
7
Trenz Electronic FPGA Modules / TE0720 LED1 and LED2
« Last post by bigguiness on February 03, 2023, 07:50:40 PM »
Can LED1 and LED2 be controlled by the user in Linux?

I have looked at the TE0720 CPLD information (Document Rev: v.140) and chapter 2.2.8 I2C to GPIO block seems to indicate they are.

But after booting my system I don not get the expected value when reading device 0x20 address 0x00:
Code: [Select]
# i2cget -y 1 0x20 0x00
0x00

The document says that the read should return 0x39.

Is there any more documentation on the CPLD I2C to GPIO block?

Also, I have asked this before, but does anyone know what device 0x21 is on I2C bus 1?
Code: [Select]
# i2cdetect -y -r 1
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f
00:          -- -- -- -- -- -- -- -- -- -- -- -- --
10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
20: 20 21 -- -- -- -- -- -- -- -- -- -- -- -- -- --
30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
40: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
50: -- -- -- -- -- -- -- 57 -- -- -- -- -- -- -- --
60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- UU
70: -- -- -- -- -- -- -- --   

Thanks
8
Trenz Electronic FPGA Modules / TE-0720 unique serial number
« Last post by bigguiness on February 03, 2023, 04:21:20 PM »
Is it possible to get the "SHA-256 authentication chip with unique serial number" in linux?

I see this when the system starts to boot:
Code: [Select]
--------------------------------------------------------------------------------
Xilinx First Stage Boot Loader (TE modified)
Release 2020.2  Feb  1 2023-17:18:15

Device IDCODE: 23727093
Device Name: 7z020 (7)
Device Revision: 2
--------------------------------------------------------------------------------
TE0720 TE_FsblHookBeforeHandoff_Custom

SoM: TE0720-03-1C  F SC REV:05
MAC: D8 80 39 DE 31 20

--------------------------------------------------------------------------------


U-Boot 2020.01 (Feb 02 2023 - 22:21:44 +0000)

CPU:   Zynq 7z020
Silicon: v3.1
DRAM:  ECC disabled 1 GiB
Flash: 0 Bytes
NAND:  0 MiB
MMC:   mmc@e0100000: 0, mmc@e0101000: 1
In:    serial@e0000000
Out:   serial@e0000000
Err:   serial@e0000000
Net:   
ZYNQ GEM: e000b000, mdio bus e000b000, phyaddr 0, interface rgmii-id

Warning: ethernet@e000b000 using MAC address from DT
eth0: ethernet@e000b000
U-BOOT for petalinux
importing env from FSBL shared area at 0xFFFFFC00
Found valid magic
## Info: input data size = 27 = 0x1B

Hit any key to stop autoboot:  0

The MAC address is being properly passed to linux:
Code: [Select]
Marvell 88E1510 e000b000.ethernet-ffffffff:00: attached PHY driver [Marvell 88E1510] (mii_bus:phy_addr=e000b000.ethernet-ffffffff:00, irq=POLL)
macb e000b000.ethernet eth0: Cadence GEM rev 0x00020118 at 0xe000b000 irq 29 (d8:80:39:de:31:20)

But I can't find any "serial number" information anywhere.

/proc/cpuinfo has this:
Code: [Select]
Hardware        : Xilinx Zynq Platform
Revision        : 0003
Serial          : 0000000000000000

And I don't see anything with a serial number under /sys/devices/soc0.

Is there a way to read the serial number from the SHA-256 authentication chip?

Thanks
9
John,

The part I missed before the 'cleanall' was:
Code: [Select]
$ petalinux-devtool finish u-boot-xlnx %{PWD}/project-spec/meta-user/ -f
$ petalinux-devtool finish linux-xlnx %{PWD}/project-spec/meta-user/ -f

I guess that copies the configuration changes to meta-user.

I wish all the Petalinux information was easier to find. Sometimes it feels like it's a "big secret" that only the "cool" people know.... Oh well... I'll figure it out eventually.
10
Trenz Electronic FPGA Modules / Re: connect TE0820 JTAG with a JTAG verilog design
« Last post by aymand on February 03, 2023, 03:29:16 PM »
Hi John,
sorry maybe I wasn't clear. I wanna use the JTAG to feed continuous data to the design after it's been programmed the first time. I know we can connect verilog design ports to the carrier pins, is it possible to connect the verilog port to this JTAG bus? Especially that they're not routed to the carrier J1 and J2 pins.
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