Print Page - TE0715 FCLK125 Signal

Title: TE0715 FCLK125 Signal
Post by: jwdonal on March 25, 2018, 04:02:34 AM

On the TE0715, why is the FCLK125 signal (generated by the SI5338) not connected to a clock-capable pin (e.g. SRCC/MRCC) on the FPGA?

Title: Re: TE0715 FCLK125 Signal
Post by: JH on March 26, 2018, 08:27:03 AM

Hi,

this clk is optional and add to a free IO which was not used. All other SRCC/MRCC was used for other purpose.
You can add Vivado constrain to use it on clk net.

br
John

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Trenz Electronic Products => Trenz Electronic FPGA Modules => Topic started by: jwdonal on March 25, 2018, 04:02:34 AM