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#91
UltraScale / TEF1002-02 with TE0820-05
Last post by harrx - May 16, 2024, 02:31:25 PMHello,
I am trying to work with the PCIe Carrier board -> TEF1002 with the TE0820 module. I am stuck at the very begining as the module is not recognized by Vivado Hardware Manager. It sees the Carrier board, but says "No devices connected to the target." I used both the Jtag/ uart and the Xilinx programmer methods.
I see 2 power supply lights on the carrier board and one blinking green light on the Module FPGA, but no Jtag connection.
I tried the TE0820 module with a custom Carrier Board, and it was detected fine as "xczu3" by Vivado H/W Manager.
Is there any Jumper setting which needs to be taken care of for the Jtag connection (I am using the default) or does it look like a connection problem. How to move forward from here.
I am trying to work with the PCIe Carrier board -> TEF1002 with the TE0820 module. I am stuck at the very begining as the module is not recognized by Vivado Hardware Manager. It sees the Carrier board, but says "No devices connected to the target." I used both the Jtag/ uart and the Xilinx programmer methods.
I see 2 power supply lights on the carrier board and one blinking green light on the Module FPGA, but no Jtag connection.
I tried the TE0820 module with a custom Carrier Board, and it was detected fine as "xczu3" by Vivado H/W Manager.
Is there any Jumper setting which needs to be taken care of for the Jtag connection (I am using the default) or does it look like a connection problem. How to move forward from here.
#92
CYC1000 community projects / Re: I present a comunity of IN...
Last post by Subcritical - May 16, 2024, 02:26:37 PMDavid Carrion create the multicore Bytednia, you can see a cold boot.
Rasberry Pi plus CYC1000.
Rasberry Pi plus CYC1000.
#93
Arrow USB Programmer2 / Step-by-step videos solving th...
Last post by Subcritical - May 16, 2024, 12:25:51 PMWe have tried to reproduce all the errors and create a sequence of videos, including the one that was most difficult to watch because the arrow blaster recording failed in a Windows developer. The solution was so simple that it was precisely the most difficult error of all.
When you move the QUARTUS II to another folder, the arrow blaster stops starting correctly.
Mainly because the Windows service looks for the enablement of the service in the path that is saved in the Windows registry.
This mistake, such a simple thing, threw us in the development group.
- Spanish -
When you move the QUARTUS II to another folder, the arrow blaster stops starting correctly.
Mainly because the Windows service looks for the enablement of the service in the path that is saved in the Windows registry.
This mistake, such a simple thing, threw us in the development group.
- Spanish -
#94
Trenz Electronic FPGA Modules / TE0710 red SysLed flashing on ...
Last post by sjoshi - May 16, 2024, 12:12:51 PMWe are working with a custom carrier board which should host a TE0710 module. On powering up the board and module, we have noticed that the red SysLED keeps flashing continuously.
It appears that there is a design flaw where we have overlooked the SC_nRST, EN1, BOOTMODE and NOSEQ inputs to the module. The EN1 and SC_nRST pins can still be used, however BOOTMODE and NOSEQ are left unconnected in the design. On pulling SC_nRST high, the red SysLed stops flashing.
Vivado cannot detect the target even if EN1 is high or low. I am afraid that BOOTMODE or NOSEQ play a crucial role in initializing the Artix 7. We are currently using a TE0790 as the programmer. The JTAG pins have been connected in a scheme similar to that used on the TE0706.
Is there a way we can still rescue the board? Can we use a custom firmware for the onboard Lattice which can overlook the NOSEQ and BOOTMODE pin states and let us access the FPGA over JTAG? The JTAGSEL signal is pulled low.
It appears that there is a design flaw where we have overlooked the SC_nRST, EN1, BOOTMODE and NOSEQ inputs to the module. The EN1 and SC_nRST pins can still be used, however BOOTMODE and NOSEQ are left unconnected in the design. On pulling SC_nRST high, the red SysLed stops flashing.
Vivado cannot detect the target even if EN1 is high or low. I am afraid that BOOTMODE or NOSEQ play a crucial role in initializing the Artix 7. We are currently using a TE0790 as the programmer. The JTAG pins have been connected in a scheme similar to that used on the TE0706.
Is there a way we can still rescue the board? Can we use a custom firmware for the onboard Lattice which can overlook the NOSEQ and BOOTMODE pin states and let us access the FPGA over JTAG? The JTAGSEL signal is pulled low.
#95
MAX1000 community projects / Re: Playing ZX Spectrum in HDM...
Last post by Subcritical - May 14, 2024, 07:16:52 PMTutorial, how to port some VHDL opensource cores from reverse U16 - Spanish - you can use translation.
It is a great excersise to knwo how to deal with the VHDL program language and you can see it here.
In next videos I'm going to share how to deal with the serilizer, because MAX10, has a diferent serializer than cyc1000.
In this case i share the ZX48 implementation in VHDL as a .QAR proyect:
https://github.com/AtlasFPGA/U16_ZX_48_Spectrum_Reloj_50MHZ_VHDL
It is a great excersise to knwo how to deal with the VHDL program language and you can see it here.
In next videos I'm going to share how to deal with the serilizer, because MAX10, has a diferent serializer than cyc1000.
In this case i share the ZX48 implementation in VHDL as a .QAR proyect:
https://github.com/AtlasFPGA/U16_ZX_48_Spectrum_Reloj_50MHZ_VHDL
#96
Trenz Electronic FPGA Modules / Disabling UART0 Console Output...
Last post by neels - May 14, 2024, 06:09:27 PMHello all,
I am working with te0720 device using 2021.2 toolchain. I have a functioning system (can build, boot linux, view bootlog via UART0 serial port and ssh into unit). I need assistance in disabling the debug UART0 console output. Currently, the device tree includes the following configuration related to the UART console output:
To disable the UART (ttyPS0) from printing console output, I have tried is to disable and remove the serial0 node (UART0) on the device tree provided by te0720 trenz reference design as shown below. But the resulting image build with the following change doesn't boot (unable to ssh into unit). The only difference between the working image and the not working image is the following change.
Could someone please provide guidance on the correct method to disable UART0 console output for te0720 SOM? Specifically, what changes should be made to ensure that console messages are not sent to ttyPS0?
Your help would be greatly appreciated!
Thank you.
I am working with te0720 device using 2021.2 toolchain. I have a functioning system (can build, boot linux, view bootlog via UART0 serial port and ssh into unit). I need assistance in disabling the debug UART0 console output. Currently, the device tree includes the following configuration related to the UART console output:
Code Select
chosen {
bootargs = "console=ttyPS0,115200 earlycon root=/dev/ram0 rw";
stdout-path = "serial0:115200n8";
};
To disable the UART (ttyPS0) from printing console output, I have tried is to disable and remove the serial0 node (UART0) on the device tree provided by te0720 trenz reference design as shown below. But the resulting image build with the following change doesn't boot (unable to ssh into unit). The only difference between the working image and the not working image is the following change.
Code Select
Index: linux/recipes-bsp/uboot-device-tree/files/system-user.dtsi
===================================================================
--- linux/recipes-bsp/uboot-device-tree/files/system-user.dtsi (revision 1999)
+++ linux/recipes-bsp/uboot-device-tree/files/system-user.dtsi (working copy)
@@ -1,5 +1,14 @@
/include/ "system-conf.dtsi"
/ {
+ axi{
+ serial@e0000000 {
+ status = "disabled";
+ };
+ };
+
+ aliases {
+ /delete-property/ serial0;
+ };
}; Could someone please provide guidance on the correct method to disable UART0 console output for te0720 SOM? Specifically, what changes should be made to ensure that console messages are not sent to ttyPS0?
Your help would be greatly appreciated!
Thank you.
#97
UltraScale / Re: TE0820-05-2AI21MA and TE07...
Last post by night_prowler - May 14, 2024, 05:03:10 PMHi John,
Can you tell me which power supply you use? Some current limit in case you use laboratory power supply?
I have tried a separate 12V supply and get the same result.
Can you try out to formate SD with only one fat32 partition and try again?
I have tried this and get the same result.
Can you also open one time Vivado HW manager and tell me if you see ARM_DAP and FPGA when you connect JTAG(one time without and one time with SD Card)?
I can see the following both with the SD Card installed and not.
Can you tell me which power supply you use? Some current limit in case you use laboratory power supply?
I have tried a separate 12V supply and get the same result.
Can you try out to formate SD with only one fat32 partition and try again?
I have tried this and get the same result.
Can you also open one time Vivado HW manager and tell me if you see ARM_DAP and FPGA when you connect JTAG(one time without and one time with SD Card)?
I can see the following both with the SD Card installed and not.
#98
UltraScale / Re: TE0820-05-2AI21MA and TE07...
Last post by night_prowler - May 14, 2024, 01:18:13 PMHi,
Thankyou for the reply.
Can you tell me which power supply you use? Some current limit in case you use laboratory power supply?
Well, interesting you should say that, the board has been wired to a Power Supply as in the image. I can try with a normal 12V power supply and see if that works.
You select barmetal Hello TE0820 Boot.bin, so Linux files are not needed in this case.
Yes, I was at the point of trying anything
Can you try out to formate SD with only one fat32 partition and try again?
I will try this as well after I have tried a different Power Supply.
Can you also open one time Vivado HW manager and tell me if you see ARM_DAP and FPGA when you connect JTAG(one time without and one time with SD Card)?
At this moment in time I haven't been able to get the HW Manager to communicate with the board at all via the JTAG... this might be my next question :-)
I will reply once more when I have tested the Power Supply and SD Card reformat, thankyou.
Thankyou for the reply.
Can you tell me which power supply you use? Some current limit in case you use laboratory power supply?
Well, interesting you should say that, the board has been wired to a Power Supply as in the image. I can try with a normal 12V power supply and see if that works.
You select barmetal Hello TE0820 Boot.bin, so Linux files are not needed in this case.
Yes, I was at the point of trying anything
Can you try out to formate SD with only one fat32 partition and try again?
I will try this as well after I have tried a different Power Supply.
Can you also open one time Vivado HW manager and tell me if you see ARM_DAP and FPGA when you connect JTAG(one time without and one time with SD Card)?
At this moment in time I haven't been able to get the HW Manager to communicate with the board at all via the JTAG... this might be my next question :-)
I will reply once more when I have tested the Power Supply and SD Card reformat, thankyou.
#99
CYC1000 community projects / Re: I present a comunity of IN...
Last post by Subcritical - May 14, 2024, 12:50:35 AMExplanation of the errors produced in the UnAMIGA core implementation, which is why the CYC1000 is very interesting to have a PAL clock 28,37516Mhz to achieve an Amiga - Minimig hdl correct description. - Spanish -
PIN DESCRIPTION:
https://github.com/AtlasFPGA/PINOUT_ATLAS_CYC1000
We choose the CYC1000 because it has two clocks one With PIN_M2 a MENS 12Mhz an one free -> PAL 28,37516Mhz.
You can see some vídeos of the development UnAMIGA AGA CORE.
TURRICAN II AGA
NEW AMIGA OS
I have stopped being involved in the development of this UnAMIGA core but other ATLAS developers continue with its development.
PIN DESCRIPTION:
https://github.com/AtlasFPGA/PINOUT_ATLAS_CYC1000
We choose the CYC1000 because it has two clocks one With PIN_M2 a MENS 12Mhz an one free -> PAL 28,37516Mhz.
You can see some vídeos of the development UnAMIGA AGA CORE.
TURRICAN II AGA
NEW AMIGA OS
I have stopped being involved in the development of this UnAMIGA core but other ATLAS developers continue with its development.
#100
UltraScale / Re: TE0820-05-2AI21MA and TE07...
Last post by JH - May 13, 2024, 09:13:00 AMHi,
3 times blinking means board set to SD Boot, but did not finished booting:
https://wiki.trenz-electronic.de/display/PD/TE0820+CPLD#TE0820CPLD-LED
Can you tell me which power supply you use? Some current limit in case you use laboratory power supply?
You select barmetal Hello TE0820 Boot.bin, so Linux files are not needed in this case.
Can you try out to formate SD with only one fat32 partition and try again?
Can you also open one time Vivado HW manager and tell me if you see ARM_DAP and FPGA when you connect JTAG(one time without and one time with SD Card)?
br
John
3 times blinking means board set to SD Boot, but did not finished booting:
https://wiki.trenz-electronic.de/display/PD/TE0820+CPLD#TE0820CPLD-LED
Can you tell me which power supply you use? Some current limit in case you use laboratory power supply?
You select barmetal Hello TE0820 Boot.bin, so Linux files are not needed in this case.
Can you try out to formate SD with only one fat32 partition and try again?
Can you also open one time Vivado HW manager and tell me if you see ARM_DAP and FPGA when you connect JTAG(one time without and one time with SD Card)?
br
John