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#71
Trenz Electronic FPGA Modules / Re: TE0820+HDMI701
Last post by PaulChang - July 02, 2024, 08:27:23 AMHi John,
Thank you for your support.
Now it can login root via terminal. But the HDMI still no output.
Any
Best Regards,
Paul
Thank you for your support.
Now it can login root via terminal. But the HDMI still no output.
Any
Best Regards,
Paul
#72
Trenz Electronic FPGA Modules / Re: FSBL hangs when initializi...
Last post by Stonebull - July 01, 2024, 03:19:16 PMOkay great, thanks for the info.
Best Regards
Best Regards
#73
Trenz Electronic FPGA Modules / Re: TE0820+HDMI701
Last post by JH - July 01, 2024, 11:32:22 AMHi,
this demo designs need also file system on SD Card. You can use Win32 DiskImager and image from te0820-ubuntu.zip to prepare SD Card with correct partitions. After partitions are created bis DiskImager, copy Boot.bin and image.ub to the fat32 partition of the SD card. Image Download:
https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0820/Reference_Design/2019.2/HDMI701
--> te0820-ubuntu.zip
br
John
this demo designs need also file system on SD Card. You can use Win32 DiskImager and image from te0820-ubuntu.zip to prepare SD Card with correct partitions. After partitions are created bis DiskImager, copy Boot.bin and image.ub to the fat32 partition of the SD card. Image Download:
https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0820/Reference_Design/2019.2/HDMI701
--> te0820-ubuntu.zip
br
John
#74
Trenz Electronic FPGA Modules / TE0820 Module Compatablity
Last post by mer - June 28, 2024, 06:29:30 PMI have a currently implemented project using TE0820-02-03CG-1EA module. Looking to move this project to TE0820-05-3AE81MA module.
The question is, will the vivado reference design for the 03CG board be valid and still work with the 3AE81MA module? At the very least might have to change RAM settings. But I'm mostly unsure about the CPLD configuration. Or am I destined to have to rebuild from the ground up from the new reference design? Thanks for any help.
The question is, will the vivado reference design for the 03CG board be valid and still work with the 3AE81MA module? At the very least might have to change RAM settings. But I'm mostly unsure about the CPLD configuration. Or am I destined to have to rebuild from the ground up from the new reference design? Thanks for any help.
#75
UltraScale / Re: Does Trenz have Master XDC...
Last post by JH - June 28, 2024, 09:25:47 AMHi,
best way is you start with our reference design:
https://wiki.trenz-electronic.de/display/PD/TE0745+Test+Board
It's for Vivado 23.2 and includes Board files for basic PS setting and some petalinux example and also prebuilt binaries to test your HW directly.
I would recommend to use 23.2 when you start, than it's easier to use our reference design with all sources.
For PL IO, you can use AMD IO planner, correct Pin Names are available in our schematics or pinout table. IO Standard for PL IOs depends on your connected periphery (the most pins goes only to simple Pin header).
Pinout table:
https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/Pinout
-->
https://shop.trenz-electronic.de/trenzdownloads/Trenz_Electronic/Pinout/TE0745_series_pinout_tracelength.xlsx
br
John
best way is you start with our reference design:
https://wiki.trenz-electronic.de/display/PD/TE0745+Test+Board
It's for Vivado 23.2 and includes Board files for basic PS setting and some petalinux example and also prebuilt binaries to test your HW directly.
I would recommend to use 23.2 when you start, than it's easier to use our reference design with all sources.
For PL IO, you can use AMD IO planner, correct Pin Names are available in our schematics or pinout table. IO Standard for PL IOs depends on your connected periphery (the most pins goes only to simple Pin header).
Pinout table:
https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/Pinout
-->
https://shop.trenz-electronic.de/trenzdownloads/Trenz_Electronic/Pinout/TE0745_series_pinout_tracelength.xlsx
br
John
#76
UltraScale / Re: Does Trenz have Master XDC...
Last post by Reymon - June 27, 2024, 02:00:26 AMHello, I am a beginner FPGA programmer, I tried to do the same, using the XDC file (Vivado 2024.1) to configure the inputs/outputs like I do with Avnet (ZedBoard) or Digilent (Nexys 4) boards. I'm wondering if you successfully created your own XDC or 'part0_pins.xml' files for the TE0820 SOM and TE0701 carrier board. If yes, could you please tell me what procedure you followed?
I have a carrier board TEB0745-02 and TE0745-02-30-1IA SOM.
I have a carrier board TEB0745-02 and TE0745-02-30-1IA SOM.
#77
Trenz Electronic FPGA Modules / Re: FSBL hangs when initializi...
Last post by JH - June 26, 2024, 12:43:48 PMHi,
yes simple remove this part of the code for PLL programming. You will not damage the board. This part is like a example in case you want to reprogramm PLL on power up. TE0715 PLL is preprogramm with following CLKS:
https://wiki.trenz-electronic.de/display/PD/TE0715+TRM#TE0715TRM-ProgrammableClockGenerator
it's the same output CLK frequence like on the example reprogramming on runtime.
br
John
yes simple remove this part of the code for PLL programming. You will not damage the board. This part is like a example in case you want to reprogramm PLL on power up. TE0715 PLL is preprogramm with following CLKS:
https://wiki.trenz-electronic.de/display/PD/TE0715+TRM#TE0715TRM-ProgrammableClockGenerator
it's the same output CLK frequence like on the example reprogramming on runtime.
br
John
#78
Trenz Electronic FPGA Modules / TE0802 as PCIe device
Last post by CM - June 24, 2024, 07:55:11 PMHi,
I am currently working on using the TE0802 as a PCIe device with the help of an M.2 to PCIe connector breakout chain with the goal of plugging the PCIe side into the edge connector on a motherboard which takes the role of the root.
Going through the pinouts of the board, my M.2 card and the PCIe connector, I can already confirm that my grounding is fine, no shorts between the voltage supplies on both sides are happening and that the TX and RX are properly handled.
However, both the PCIe host machine as well as the TE0802 will have a conflicting reference clock on the connection.
I would like to stop the clock generator on the TE0802 to apply its signal to the M.2 connector.
There are two paths I currently see:
1) Remove the decoupling caps on the output of the CDCI6214 (C126/C172) to physically disconnect the clock generator from the connector.
I would like to avoid this because this setup will be replicated fairly often.
2) Reprogram the CDCI6214 to set the output of Channel 4 (Y4P/Y4N) to a high impedance state.
So my question boils down to:
Is it possible to reprogram the CDCI6214 on the TE0802 to stop the generation of the SSD_RCLK and if so, how would I achieve this?
Thanks a lot
Christopher
I am currently working on using the TE0802 as a PCIe device with the help of an M.2 to PCIe connector breakout chain with the goal of plugging the PCIe side into the edge connector on a motherboard which takes the role of the root.
Going through the pinouts of the board, my M.2 card and the PCIe connector, I can already confirm that my grounding is fine, no shorts between the voltage supplies on both sides are happening and that the TX and RX are properly handled.
However, both the PCIe host machine as well as the TE0802 will have a conflicting reference clock on the connection.
I would like to stop the clock generator on the TE0802 to apply its signal to the M.2 connector.
There are two paths I currently see:
1) Remove the decoupling caps on the output of the CDCI6214 (C126/C172) to physically disconnect the clock generator from the connector.
I would like to avoid this because this setup will be replicated fairly often.
2) Reprogram the CDCI6214 to set the output of Channel 4 (Y4P/Y4N) to a high impedance state.
So my question boils down to:
Is it possible to reprogram the CDCI6214 on the TE0802 to stop the generation of the SSD_RCLK and if so, how would I achieve this?
Thanks a lot
Christopher
#79
Trenz Electronic FPGA Modules / Re: FSBL hangs when initializi...
Last post by Stonebull - June 24, 2024, 01:45:51 PMHello Waldi,
sorry for my late reply, I did not see your message earlier.
I am still using the Vivado Version 2019.1 for a reason. A while ago a colleague of mine tried using the Trenz SOMs with the newest reference design, the 2022.2 which resulted in extreme problems during debugging (Stepping issues, breakpoints setting failed,...).
On his request for support, Mr. John Hartfiel could not provide us a solution, apart from telling us to go ask Xilinx for support on their faulty toolchain. Unfortunately AMD repied that they cannot give us support on outdated Tools (Vivado at the time released version 2023.x). So we were stuck, as the newest Reference Design from Trenz was (and still is) using only Vivado 2022.2.
My solution for the current problem of not being able to boot from flash anymore, was to rebuild the project from scratch from a working reference design.
Can you tell me if it is save to not program the Si5338 Clock Generator at all, in order to use the I2C1 for other stuff?
And how may I overcome the booting issue of the FSBL? Can I skip the section that blocks entirely without damaging something?
sorry for my late reply, I did not see your message earlier.
I am still using the Vivado Version 2019.1 for a reason. A while ago a colleague of mine tried using the Trenz SOMs with the newest reference design, the 2022.2 which resulted in extreme problems during debugging (Stepping issues, breakpoints setting failed,...).
On his request for support, Mr. John Hartfiel could not provide us a solution, apart from telling us to go ask Xilinx for support on their faulty toolchain. Unfortunately AMD repied that they cannot give us support on outdated Tools (Vivado at the time released version 2023.x). So we were stuck, as the newest Reference Design from Trenz was (and still is) using only Vivado 2022.2.
My solution for the current problem of not being able to boot from flash anymore, was to rebuild the project from scratch from a working reference design.
Can you tell me if it is save to not program the Si5338 Clock Generator at all, in order to use the I2C1 for other stuff?
And how may I overcome the booting issue of the FSBL? Can I skip the section that blocks entirely without damaging something?
#80
EDDP-EDPS Support / TE0950 Power consumption / Hea...
Last post by dje666 - June 24, 2024, 12:53:07 PMDear Forum,
Can anyone tell me the core temperature of the Versal device fitted to this TE0950 dev-kit when all 8 XCVRs are very active (preferably with x4 PCIe and QSFP Links running).
In my Artix US+ design it's the 8 XCVRs that are burning power and generating heat, and I need to know if the Versal family might be a lower power alternative.
Regards,
DJE666
Can anyone tell me the core temperature of the Versal device fitted to this TE0950 dev-kit when all 8 XCVRs are very active (preferably with x4 PCIe and QSFP Links running).
In my Artix US+ design it's the 8 XCVRs that are burning power and generating heat, and I need to know if the Versal family might be a lower power alternative.
Regards,
DJE666