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Trenz Electronic GmbH Support Forum

Trenz Electronic Products => Trenz Electronic FPGA Modules => Topic started by: dave74321 on May 21, 2018, 04:30:10 PM

Title: TE0720 board initialization file
Post by: dave74321 on May 21, 2018, 04:30:10 PM
https://wiki.trenz-electronic.de/display/TE0720/DDR3+SDRAM

states "Setting the DDR3 configuration for the TE0720 is straightforward...Optimal delays are not zero, so it is recommended to load the board initialization file were correct delays are pre-defined."

Where is the "board initialization file" to obtain the training delay values? (for TE0720-03-1CFA)

Thanks
Title: Re: TE0720 board initialization file
Post by: JH on May 22, 2018, 11:09:21 AM
Hi,
it's included into the reference design, for different vivado versions:
PS: your document link is from an older documentation. We put this to our archive to until we have transferred a important notes from this older documentation.
To get all sources and documents, follow links from:brJohn
Title: Re: TE0720 board initialization file
Post by: dave74321 on May 30, 2018, 02:26:48 PM
Thank JH for the links.

I generated a Vivado example design so that I could see the training delay values that were used.

I now use those in my design - I'll ignore all the critical warnings I now get (e.g. Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.001 . PS DDR interfaces might fail when entering negative DQS skew values.)

Title: Re: TE0720 board initialization file
Post by: JH on May 30, 2018, 03:00:53 PM
Hi,


set DQS to zero. It's only for initial training and ddr is closed to FPGA. Negative value works also. In one of the older vivado versions neg. value was allowed.
I will change this on the board part files in one of the next design updates.

br
John

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