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1
Trenz Electronic FPGA Modules / TE0720 board initialization file
« Last post by dave74321 on Today at 04:30:10 PM »
https://wiki.trenz-electronic.de/display/TE0720/DDR3+SDRAM

states "Setting the DDR3 configuration for the TE0720 is straightforward...Optimal delays are not zero, so it is recommended to load the board initialization file were correct delays are pre-defined."

Where is the "board initialization file" to obtain the training delay values? (for TE0720-03-1CFA)

Thanks
2
Trenz Electronic FPGA Modules / Re: Schematic Te0712 200 2C3 U.FL-R-SMT-1????
« Last post by lantionik on May 18, 2018, 04:29:06 PM »
Thanks for the help!
3
MAX1000 community projects / Re: USB interface use by NIOS apps
« Last post by JH on May 17, 2018, 02:48:18 PM »
Hi,

thank you very much for this information.

I don't know why it works on my place, maybe this was set correctly during my Xilinx JTAG driver installation.  We use second FTDI port for uart also with our JTAG programmer for Xilinx devices.

I've forward this notes to the Arrow Programmer driver/setup files developer, so I hope they can solve this issue during the next update.

br
John
 
4
Trenz Electronic FPGA Modules / Re: TE0726 boot problem
« Last post by JH on May 17, 2018, 10:18:58 AM »
Hi,
i've upload new version.My additional changes for 128MB variant, this must be done manually after HDF import, if you use the template for all variants:to your questions:

1. we provide board part files (included into the reference design), you can export this tcl with Vivado after you has run board automation for IP. So you can also export your additional PS changes.
2.memory size will be set from HDF import if you create a new project, you can reduce manually, if you need space for other purpose.

3. https://wiki.trenz-electronic.de/display/PD/TE0726+Test+Board#TE0726TestBoard-Programmingthis small package can primary only boot from QSPI, but secondary boot, like with Uboot can us SD to load linux for example

3.(net boot + zc702 ;-)) this will be not reduced automatically, so for very small RAM you must do manually, i used half size (https://wiki.trenz-electronic.de/display/PD/TE0726+Test+Board#TE0726TestBoard-Config)See also https://www.xilinx.com/support/answers/59853.htmlXilinx create default config always from here evaluation boards, over HDF import this will be overwrite. Unfortunately not always all correctly. And zc702 is only the name from the template, you find sources on xilinx git.I've add all changes after HDF import on: https://wiki.trenz-electronic.de/display/PD/TE0726+Test+Board#TE0726TestBoard-SoftwareDesign-PetaLinuxSometimes this will changed during Vivado/petalinux version, but the basics are the same.

4. depending what you want to do, we didn't changed on our example


So summary:Net boot offset was my mistake for this small variant (I've no 128MB on place, so I can't test). I've documented all changes i've done after create project with the exported HDF on:
PS: Some documents links:For links with "xilinx20xx_x" you should always use the same UG like your installed vivado/petalinux version.

br
John
5
Trenz Electronic FPGA Modules / Re: TE0726 boot problem
« Last post by javier.reyes.g on May 16, 2018, 04:32:50 PM »
Hi JH

I will try to build it my myself, following the material available. I still find some unclear things...

1. If I want to set the presets of a Vivado project (following as an example this guide https://eewiki.net/display/Motley/Getting+Started+with+the+ZynqBerry, which is the most clear procedure I have found), the TCL file provided there containing the defaults presets for the Zynqberry 726-03M (ZynqBerryPSDefault.tcl) would still be applicable? Of course, modifying the memory size:

Before
Code: [Select]
CONFIG.PCW_DDR_RAM_HIGHADDR {0x1FFFFFFF}  \

After
Code: [Select]
CONFIG.PCW_DDR_RAM_HIGHADDR {0x07FFFFFF}  \

If not, is there any similar file provided by Trenz? Or the only way is to use the reference design project and scripts (which IMHO is more confuse to use and do not facilitate the comparison to the workflow described by Xilinx)?

2. To configure the memory size in petalinux, I see in the menu:

Code: [Select]
Subsystem AUTO Hardware Settings
    Memory Settings
        (0x0) System memory base address
        (0x8000000) System memory size (NEW)
        (0x0) kernel base address
        (0x400000) u-boot text base address offset to memory base address

Should the 2nd element (System memory size) be changed to 0x07FFFFFF for 128MB?
The 4th also should be adjusted? I have looked around in internet but I cannot find anything related.

3. There is nothing mentioned in the instructions of the reference design, but it is shown in the above mentioned tutorial: In petalinux-config menu:

Code: [Select]
Advanced bootable images storage Settings
    boot image settings
    u-boot env partition settings
    kernel image settings
    jffs2 rootfs image settings
    dtb image settings

As far as I understand, the boot image settings need to be changed (by default shows image storage media as primary SD, but should be primary flash, right?).

Other configs that are not mentioned:

jffs2 rootfs image settings - This is by default at primary flash. Should the right config be different? The names (partition and file) are also specified as jffs2 and rootfs.jffs2 respectively. Is the rootfs generated with this config?

dtb image settings - This is by default from boot image. What I have seen is that the device tree is compiled by petalinux, and that for the use of the Ethernet interface (usb-to-ethernet hub) it is necessary to add some lines to the system-top.dtsi file before building the image. Should this item be changed to read the device tree from SD, and copy the system.dtb generated by petalinux to the SD along with the image.ub?

3. The petalinux-config menu shows:

Code: [Select]
u-boot Configuration
    (zynq_zc702_config) u-boot config target
     (0x10000000) netboot offset

On this part is that you mention I should set the memory size, which is unclear... Should I set this value to the max size of the address for 128MB (0x07FFFFFF)? If so, what relation is there between this and the memory size in the Subsystem Auto Hardware Settings?

Also, this u-boot config target is showing a zc702_config. Is this a correct setting? I thought the ZC702 was an evaluation board from Xilinx using the 7Z020 device, which is quite different to the 7Z010 that the zynqberry 726 uses.

4. On the same config menu says:

Code: [Select]
Image Packaging Configuration
    Root filesystem type (INITRAMFS)
    (image.ub) name for bootable kernel image
    (0x1000) DTB padding size

Is it necessary here to let the default config? I would think it needs to match the rootfs selected before (JFFS2). Or is the right one the INITRAMFS? If I were to use a specific rootfs, as explained in the guide I linked above (debian or ubuntu), Should the DTB be modified somehow?

This is the type of information that should be clarified in the documentation of the reference design, as the default options do not work, and this are selectable according to the hardware (Trenz side).

I appreciate any comment on this questions, as it might seem that are too many. I do not intend to make other to do my work, but simply obtain help that I cannot find anywhere.

Regards
6
Trenz Electronic FPGA Modules / Re: TE0726 boot problem
« Last post by JH on May 16, 2018, 09:45:02 AM »
Hi,
it was my mistake. Netboot offset is not set automatically on HDF import. I will regenerate the files and will upload new version.
I let you know, when it's finished.
Or you generate petalinux by yourself

br
John
7
MAX1000 community projects / Re: USB interface use by NIOS apps
« Last post by patk on May 15, 2018, 04:49:36 PM »
I finally figured out the second port on the FTDI driver. When the driver first installs with the Arrow blaster only the JTAG com port is turned on and shows in the device/serial ports. I found out that I had to manually open up the FTDI driver and enable a second VCP. This may have been obvious to someone familiar with the FTDI driver and the Arrow blaster, but new to me and its not easily found or documented.

I did get the second com port to work with the MAX1000.
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Trenz Electronic FPGA Modules / Re: TE0726 boot problem
« Last post by JH on May 15, 2018, 03:26:41 PM »
Hi,

maybe this is may mistake. I've no TE0726 with 128MB on place. I found:
So I didn't change correctly all petalinux settings for smaller RAM size. I will check sources.

br
John
9
Trenz Electronic FPGA Modules / Re: TE0726 boot problem
« Last post by javier.reyes.g on May 15, 2018, 03:20:52 PM »
Hi

It looks like a nightmare... I just tried the prebuilt image (by zero dowloaded the test_board project, created the project with the scripts, launched SDK with the TE TCL command, programmed flash with prebuilt/boot_images/r/BOOT.BIN and the special FSBL in prebuilt/software/r/zynq_fsbl_flash.elf, copied the prebuilt/os/r/image.ub to the SD card, and now this happening at boot:

Code: [Select]
0
Device: sdhci@e0101000
Manufacturer ID: 9c
OEM: 534f
Name: USD00
Tran Speed: 50000000
Rd Block Len: 512
SD version 3.0                                                                   
High Capacity: Yes                                                               
Capacity: 15 GiB                                                                 
Bus Width: 4-bit                                                                 
Erase Group Size: 512 Bytes                                                       
reading image.ub
9559496 bytes read in 679 ms (13.4 MiB/s)
## Loading kernel from FIT Image at 10000000 ...
   Using 'conf@1' configuration
   Verifying Hash Integrity ... OK
   Trying 'kernel@0' kernel subimage
     Description:  Linux Kernel
     Type:         Kernel Image
     Compression:  uncompressed
     Data Start:   0x100000d4
     Data Size:    3788176 Bytes = 3.6 MiB
     Architecture: ARM
     OS:           Linux
     Load Address: 0x00008000
     Entry Point:  0x00008000
     Hash algo:    sha1
     Hash value:   c1514747fb4833af6a63f18f4cd2debf58255f62
   Verifying Hash Integrity ... sha1+ OK
## Loading ramdisk from FIT Image at 10000000 ...
   Using 'conf@1' configuration
   Trying 'ramdisk@0' ramdisk subimage
     Description:  ramdisk
     Type:         RAMDisk Image
     Compression:  uncompressed
     Data Start:   0x103a086c
     Data Size:    5755241 Bytes = 5.5 MiB
     Architecture: ARM
     OS:           Linux
     Load Address: unavailable
     Entry Point:  unavailable
     Hash algo:    sha1
     Hash value:   a283296efdb5a1a320bc315e1416a1626b8395bf
   Verifying Hash Integrity ... sha1+ OK
## Loading fdt from FIT Image at 10000000 ...
   Using 'conf@1' configuration
   Trying 'fdt@0' fdt subimage
     Description:  Flattened Device Tree blob
     Type:         Flat Device Tree
     Compression:  uncompressed
     Data Start:   0x1039cf58
     Data Size:    14435 Bytes = 14.1 KiB
     Architecture: ARM
     Hash algo:    sha1
     Hash value:   82fa3f697766b4849d08daf8df89981ea35cdd68
   Verifying Hash Integrity ... sha1+ OK
   Booting using the fdt blob at 0x1039cf58
   Loading Kernel Image ... OK
   Loading Ramdisk to 06dc6000, end 07343169 ... OK
ERROR: image is not a fdt - must RESET the board to recover.
FDT creation failed! hanging...### ERROR ### Please RESET the board ###

Any idea what is happening?

Thanks in advance

Regards
10
Trenz Electronic FPGA Modules / Re: TE0726 boot problem
« Last post by JH on May 15, 2018, 02:22:10 PM »
Hi,

you must use TE0726-03R --> ID 2
I know, sometimes the product name will be changed, but product is nearly the same.
I've some basic documentation:
And also add a Wiki description, to make this a little bit clearer:It's not perfect yet, but i try to make it a little bit clearer  from time to time.
One design project for all variants instead of single project for every assembly variant + revision is the only way to handle all this boards at the moment. There are to much variants to support one or two design updates for newer vivado versions per year, if i generate a single project for all. List of currently available design, see:To your memory question. Memory is set on PS IP  --> We provide default setting with the board part files.
After export of the HDF from the design, SDK or Petalinux project can use the information to set correct size. Size can be also reduced on petalinux config( in case you need a part for other purpose).
br
John
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