Hi,
Please help. I'm trying to bring-up TE0715 SoM's eth1 on TE0706 carrier. eth0 is working fine. The jack's LED0 is blinking slowly, while LED1 is dark. The GMII_to_RGMII's link_status is 0.
Linux sees the eth1 as generic:
macb e000b000.ethernet eth0: Cadence GEM rev 0x00020118 at 0xe000b000 irq 147 (00:0a:35:00:1e:53)
Marvell 88E1510 e000b000.etherne:00: attached PHY driver [Marvell 88E1510] (mii_bus:phy_addr=e000b000.)
libphy: MACB_mii_bus: probed
macb e000c000.ethernet eth1: Cadence GEM rev 0x00020118 at 0xe000c000 irq 148 (00:0a:35:00:22:01)
Generic PHY e000c000.etherne:08: attached PHY driver [Generic PHY] (mii_bus:phy_addr=e000c000.etherne:)
Register dump shows all 0 on eth1:
root@eth1:~# ethtool -d eth0
Offset Values
------ ------
0x0000: 1c 00 00 00 42 a5 0e 01 06 00 00 00 00 00 00 00
0x0010: 48 27 04 3f d0 12 04 3f 00 00 00 00 09 f3 ff 07
0x0020: 5a 00 00 00 5a 00 00 00 d0 12 04 3f d0 12 04 3f
0x0030: 00 00 00 00 10 0f 18 00 00 00 00 00 00 00 00 00
root@eth1:~# ethtool -d eth1
Offset Values
------ ------
0x0000: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Does this mean the MDIO interface has problem? What should I look at next? Thanks!
Hi,
did you connect everything correctly on PL?
For IO LOC constrain, see TRM, Schematics or our Master Pinout viewer:
- https://wiki.trenz-electronic.de/display/PD/TE0715+Resources
- https://wiki.trenz-electronic.de/display/PD/TE0706+Resources
- https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/Pinout
We have a 2016.2 reference design for TE0720 online, you can use this as reference:
- https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/TE0720/Reference_Design/2016.2/carrier_te0706_eth (https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/TE0720/Reference_Design/2016.2/carrier_te0706_eth)
br
John
Thanks for the reply.
I have some further questions: On the TE0715, the ETH0 PHY's CONFIG and LED1 are connected to Lattice FPGA. What does it do? There is no such option for the PHY on the TE0706 carrier, not through the Zynq without soldering wires. How to compensate for that? The PHY's datasheet online does not cover 1.8v version. Is there an updated version? Thanks.
I checked the TE0720_ETH reference design. It has the same problem that puzzles me. The ETH_CONFIG is tied to 1, so the PHY address is 00001. However, the gmii_to_rgmii has PHY address 8. In u-boot, I'm getting
Zynq> mdio list
eth0:
0 - Marvell 88E1510 <--> ethernet@e000b000
eth1:
1 - Marvell 88E1510 <--> ethernet@e000c000
Zynq> mii device eth1
Zynq> mii info
PHY 0x01: OUI = 0x5043, Model = 0x1D, Rev = 0x01, 1000baseT, FDX
PHY 0x08: OUI = 0x0000, Model = 0x00, Rev = 0x00, 10baseT, HDX
Then when linux boots, the eth1 fails because the PHY does not respond to address 8.
What am I missing? Thanks.
Never mind the last reply. The PHY 0x08 is for the gmii_to_rgmii itself. So those all look good.
The error I'm having now is "ARP Retry count exceeded" when tftpboot.
Hi,
CPLD IOs for ETH0:
- CONFIG is set to GND
- LED goes back to FPGA over X1
Wiki descriptions is on my todo list.
Try at first only one ETH (PL ETH to TE0706 PHY). Petalinux has sometime problems with two and automatically generated settings.
So did you connect all signals correctly? Also MDIO? Did you check ETH Reset? Is this set on your design?
br
John
Yes, I checked the connections many time. During u-boot, the eth1 link is up. Where does eth1 get its MAC address, if not random?
Hi,
eht0 and eth1 works with UBoot? If yes, check device tree, maybe entry for second eth phy is not set.
br
John
No, only eth0 works with u-boot "naturally"; eth1 never works in u-boot. Even when eth0 is disable from PS, and eth1 becomes eth0, I still get "ARP Retry count exceeded" error.
Hi,
- Phy not found
- PHY reset timed out
- https://community.nxp.com/thread/331776 (https://community.nxp.com/thread/331776)
Did you connect Reset IO correct?
Did you add device tree entry. On TE0720 in 2016.2 it was:
- https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/TE0720/Reference_Design/2016.2/carrier_te0706_eth (https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/TE0720/Reference_Design/2016.2/carrier_te0706_eth)
&gem0 {
phy-handle = <&phy0>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: phy@0 {
compatible = "marvell,88e1510";
device_type = "ethernet-phy";
reg = <0>;
};
};
};
/*
&gem1 {
gmii2rgmii-phy-handle = <&gmii_to_rgmii_0>;
phy-mode = "gmii";
status = "okay";
phy-handle = <&phy1>;
xlnx,ptp-enet-clock = <0x69f6bcb>;
ps7_ethernet_1_mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
gmii_to_rgmii_0: phy@8 {
device_type = "ethernet-phy";
reg = <8>;
};
phy1: phy@1 {
compatible = "marvell,88e1510";
device_type = "ethernet-phy";
// reg = <1>;
reg = <0>;
};
};
};
But try at first only with TE0706 ETH only. Petalinux has always (workarounds depends petalinux version ) some problems to start both automatically.
br
John