I have been having problems using ILA with systems clocked by the PS and I think is because of that.
Is there any clock for the PL?
Hi,
PS must be programmed to get PS-PL CLK available. This will be done by FSBL, which is generated by your XSA where these CLKS are enabled.
In case you use Linux, linux files must also be regenerated otherwhise Linux will disable them again.
SI5338 is not preprogrammed, to get SI5338 CLKs you need FSBL --> see Starterkit reference design
br
John
Let me rephrase the question: what is the simplest way to have a clock to the PL with the minimum (ideally none) implication of the PS?
Simple answer: Use a native FPGA.
Alternatively use some FMC card which provides CLKs to FPGA IOs.
Simple way I would suggested, configure PS-PL IOs like you want in your Vivado Design, export XSA, generate FSBL and boot.bin. Put Boot.bin on SD and boot from SD, now you can reload bitstream over vivado and the predefined PS-PL CLKs are available with the speed which was selected on your Boot.bin design.
br
John