Recent Posts

Pages: [1] 2 3 ... 10
1
Hi,
you should add following to the device tree:
Code: [Select]
&sdhci1 {
    // disable-wp;
    no-1-8-v;
 
};

this should help to fix this issue with some SD Cards.

We have include this to our 2017.4 reference design:

br
John
2
On the Trenz carrier board this works fine (both u-boot and kernel can access the SD card).  However, when booting an almost identical kernel build on our custom I/O carrier board we can not access the SD card once the kernel has been booted.  It can however, boot (via U-boot) from the SD card.  Our custom I/O carrier board routes the SD pins through the FPGA.  We saw some documentation about reducing the frequency Tran Speed from 50000000 down to 20000000 (via device tree configuration).  However, we are unsure if that update has produced any actual changes. 
When booting on the Trenz carrier board, we eventually see the following msgs during kernel boot (excerpt):
(on this h/w it works)
===============
can: controller area network core (rev 20120528 abi 9)
NET: Registered protocol family 29
mmc0: new high speed SDHC card at address aaaa
can: raw protocol (rev 20120528)
mmcblk0: mmc0:aaaa SL32G 29.7 GiB
can: broadcast manager protocol (rev 20120528 t)
mmcblk0: p1

However, when booting the kernel on our custom I/O carrier board we see the following msgs at around the same boot sequence (excerpt):
This h/w it doesn't work!
=================
mmc0: error -110 whilst initialising SD card
NET: Registered protocol family 29
can: raw protocol (rev 20120528)
can: broadcast manager protocol (rev 20120528 t)
....
INIT: version 2.88 booting

mmc0: error -110 whilst initialising SD card
mmc0: error -110 whilst initialising SD card

usb 1-1: new high-speed USB device number 2 using ci_hdrc
mmc0: error -110 whilst initialising SD card

I've attached output from a printenv (U-boot) and the kernel boot sequence.
I've also attached the device tree update with the updated transpeed (which didn't help), and a couple of the linux kernel configs (from the petalinux project):
/subsystems/linux/configs/u-boot/platform-auto.h
/subsystems/linux/configs/u-boot/platform-top.h

Any help on getting our SD card working within the kernel on our carrier I/O card would be most appreciated!

3
Yes,
if PS is not needed pure FPGA board is a better choice.

If you start with ZynqBerry,  use our reference design at first. I will try to create a first 2017.4 design with wiki description a little earlier.

br
John
4
I see, thank you. I will do these simple examples on a simpler board (without a PS) then and possibly come back to this board later! :)
5
Hi,
on normal design flow yes. For example Zynq PS is need to load programming file from flash. There are much ways to start design.

You can do following (easy way but maybe not complete correct way):
  • Create Design with our Board Part (for exampe 2017.1 design or wait for 2017.4)
  • Remove all IPs (only Zynq must be there)
  • Disable PS-PL AXI (On Zynq PS setup)
  • Enable all 4 PS-PL CLKs and set your preferred CLK frequency
  • Generate Design
  • export hdf to SDK
  • generate fsbl and boot.bin
  • configure flash
  • --> on power on PS is initialised by Flash design and you can overwrite PL part with bitfile programming, which used this clks
br
John
6
Thank you for your help. Am I understanding you correctly if I interpret you as saying that this board, with the Zynq chip, is not usable as "plain" FPGA without an ARM core. I.e., I must initialize and configure the ARM core to be able to use the FPGA part of the chip (because there's no clock available otherwise)? For example, here I would like to just build the LED example, not build an AXI4 peripheral (to the ARM core I assume) as the wiki links tells me to do.
7
Trenz Electronic FPGA Modules / Re: TE-0720 TCL - how to Run only PS Application update???
« Last post by JH on January 19, 2018, 09:55:02 AM »
Hi,
we have new 2017.4 reference design with wiki description:
If you do not change the vivado design, you can recreate Boot.bin with SDK. You found some basic notes on the following link:A description of the TE scripts is on:But normally it's only need to create the project with this scripts. Other features of this scripts are optional (scripts are only a automation of some parts of the xilinx recommended design flow).

Other Links to Xilinx Documentation on:br
John




8
Hello,

we have some reference design to start (include board part files for correct PS settings on vivado):
2017.4 reference design is in preparing with wiki documentation instead of instruction on the download page.

You should use Vivado Block Design (in the most cases easier). You can create own Block Design IPs, which can be written in verilog.
You find some xilinx reference on:
Search for UG number and select your Vivado Version on the URL of the document or use Xilinx DocNav.


On Zynq, PS must be initialized to get PS CLKs running. Normally this is done by FSBL. Configure Bitfiles does not initialise PS part.



For XDC: We provide a master pinout Excel Viewer (only Loc constrain)/Generator :We have also Schematics available:
br
John


9
Hello, I'm trying to get the simplest possible Verilog program to run on my te0726-03m. More specifically, I'm trying to follow https://www.beyond-circuits.com/wordpress/tutorial/tutorial1/. The problem I have is about pin assignments and io-standards.

I noticed that other boards have useful pre-built XDC files, such as e.g. https://github.com/Digilent/digilent-xdc. Does the te0726-03m have something similar, or does one have to go through some (hidden) data sheet somewhere to figure out which io-standard to assign various pins?

I also noticed this wiki page: https://wiki.trenz-electronic.de/display/PD/LED+Blinky+Tutorial. There it is said that:

Quote
In Zynq System the main System Clock is connected PS (Processing Subsystem) and is not directly available to the PL (Programmable Logic - FPGA) unless the PS has enabled it during FSBL boot process. So if we have a generic Zynq Board then we can not expect to have clocks available to the FPGA until the Processing system has provided them. There may be clocks available to the PL that are active when the PS is not booted but this not a requirement.

If our goal is to make a LED to blink (from PL in Zynq Device), then the safest way is to use FPGA Configuration Master Clock this clock is always available and accessible in the same way, we do not need to know any specifics to the board we have and we do not depend on PS init done by FSBL.

This might be a problem here, because I have not configured the PS in any way (because I was hoping one wouldn't have to just to get the simplest possible program to run). Is there some clock one can use on the te0726-03m without configuring/starting/interacting/understanding the PS?

Lastly, I don't have any LEDs ... I was hoping that the Vivado IDE would be able to do something similar to what is done in the end of this video (when the board is plugged in over USB to my computer, without external extra JTAG components): https://www.youtube.com/watch?v=TlWlLeC5BUs. But I haven't been able to get that far because Vivado do not want to generate a bitstream because of missing pin assignments.

So concretely I just need to understand what clock to use, and find some pins that can be used in some Vivado GUI similar to what is seen in the linked YouTube video (include which io-standard to use everywhere). Does anyone have any pointers? Thanks.
10
Open source hardware / Re: zynqberry tutorial for dummies
« Last post by JH on January 17, 2018, 11:17:33 AM »
Hi,

sorry, I didn't tried out this, so I can only send some link:
I used 2017.1 links, because our current available board part files are 2017.1. 2017.4 will be the next update from our side.

I hope this links helps.
Best regards
John
Pages: [1] 2 3 ... 10