I am looking for an example, or other hints, to communicate between the PL and PS together with the (debian) linux installation.
Have searched and looked through the forum, as well as done general internet searches, but have not been able to find any VHDL code with corresponding C code for the PS side.
I've gathered that I should probably use some register access via axi4-lite, but then I'm stuck. Looking at vivado/zynqberrydemo2.srcs/sources_1/bd/zsys/hdl/zsys_wrapper.vhd of zynqberrydemo2 after setting it up, I am not able to figure out if any of the top-level signals are what I should be looking for. On a side note, I am also wondering how much the current PL code can be scaled down, with linux still running? But that is later issue.
(I suspect that I am at a slight disadvantage, since I prefer the command line, and the FPGA programming I have done so far have used the xilinx tools (xst etc) from the command line... ;))
Some background and a another question at the end:
I have a rather large (20k lines) VHDL code which currently run on virtex4 and virtex5 FPGAs, with no other dependencies than the virtex DSP and BRAM blocks. It performs live trigger processing and monitoring for physics experiments and use and produce I/O signals. It has some companion programs running on a CPU, which currently communicate using register access (memory mapped, but that could be modified) over a VME bus.
It is an great advantage to have a full gnu/linux system with all development tools natively, so I am very happy indeed with the debian installation for the Zynqberry, having make and gcc available. The companion programs compiled directly (with dummy register access).
With the companion structure CPU and FPGA of my existing system, the zynq (and Zynqberry as test system) looks very promising as I understand that it is possible to reprogram the PL from the PS, while the PS continues to run. This would be a great advantage.
My plan so far, where I am currently at step 7 (possibly 3/6, see note below):
1) Make Zynqberry boot from SD.
2) Boot the Zynqberry with linux.
3) Reload the FPGA bitstream.
4) Setup the zynqberrydemo2 project in vivado.
5) Produce a new bitstream.
6) Load the new bitstream.
7) Verify that new bitstream is running.
8 ) Communicate PS <-> PL.
9) Adapt and port VHDL code to get it running on the Zynq.
10) Make some GP I/O pins on the Zynqberry interface with the FPGA code.
Notes:
3) and 6): After doing cat zynqberrydemo2.bit > /dev/xdevcfg (with the prebuilt ./prebuilt/hardware/te0726_m/zynqberrydemo2.bit) and cat zsys_wrapper.bit > /dev/xdevcfg with the bitstream from 5) the green LED on the Zynqberry blinks. Does this mean that the loaded bitstream is actually running the PL, or just that it was loaded?
Hello,
to overload PL from Linux you should be sure that Linux don't use any resources from PL at this time. There should be no bus access and DMA transfers, that is not easy to make in standard linux configuration.
Other way is to use partial reconfiguration, this way you can have fixed PL part with PS-PL interface and dynamic reconfigurable part with user logic.
Best regards
Oleksand Kiyenko
But normal memory access and network operations from Linux is ok?
Only if one uses some FPGA elements like video en/decoder or FPGA audio there might be a problem?
The only FPGA logics I intend to use does talk to applications in linux that I have control of, so would just have to shut them down before reconfiguring the PL.
Hello,
yes, you can use all PS blocks/interfaces, but there should be no PL bus access while PL part is not programed. Single register read or write transfer at this time will hang entire system.
Best regards
Oleksandr Kiyenko