Print Page - TE0722 I/O RESET AND DIFF CLOCK PORT

Title: TE0722 I/O RESET AND DIFF CLOCK PORT
Post by: jess_astrid on October 11, 2019, 10:24:02 PM

Hi, we followed the steps of the RGB example https://hackaday.io/project/6786/logs?sort=newest&page=2.
The example doesn't show the constraints definition, so we don't know what to set in the I/O ports for diff_clock_rtl and rst.reset_rtl. We search in the schematics but didn't find something. Those are external? Is fine to set user I/O Std Ports? Thanks

Title: Re: TE0722 I/O RESET AND DIFF CLOCK PORT
Post by: JH on October 14, 2019, 12:13:47 PM

Hi,
don't know the example you has link and it's very old.
And I don't know why you need diff CLK Buffer for external CLK and external reset. You can use Zynq PS-PL ClK and Zynq Reset.

We provide an example Design:
https://wiki.trenz-electronic.de/display/PD/TE0722+Test+Board
my example the RGB LEDs can be controlled via Vivado HW Manager and simple VIO Core:
https://wiki.trenz-electronic.de/display/PD/TE0722+Test+Board#TE0722TestBoard-VivadoHWManager

br
John

Trenz Electronic GmbH Support Forum

Trenz Electronic Products => Trenz Electronic FPGA Modules => Topic started by: jess_astrid on October 11, 2019, 10:24:02 PM