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Trenz Electronic FPGA Modules / Re: QSPI and SD-card boot Arduzynq
« Last post by sonycman on November 17, 2018, 06:44:15 PM »
Why we just can't define MMC_SUPPORT in FSBL, it then should search the SD CARD for boot.bin and load the fabric and application from it?
Does it not?
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Trenz Electronic FPGA Modules / Re: TE0715 Mode2 (MIO4) signal (which B2B pin?)
« Last post by jwdonal on November 15, 2018, 03:35:36 AM »
https://wiki.trenz-electronic.de/display/PD/TE0715+CPLD

After finding the above page I believe that we figured out which pin it is. Under the "Boot Mode" section the page would seem to indicate that the Lattice CPLD (U26) MODE2_R output signal on pin 17 is controlled by the MODE signal input on CPLD pin 30.

Back tracking the MODE signal to the JM1 B2B connector it indicates on the TE0715 schematic that it is connected to JM1 pin 32.

So toggling JM1 pin 32 high or low will allow us to select between SD card or QSPI for booting. Is that correct?
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Trenz Electronic FPGA Modules / Re: TE0715 Mode2 (MIO4) signal (which B2B pin?)
« Last post by jwdonal on November 15, 2018, 01:57:39 AM »
We have done further research on this. We have confirmed that the TE0703 baseboard DIP switch S2-4 does indeed dynamically control Zynq pin MIO4 (MODE2_R) on the TE0715 module. The connectivity path for DIP S2-4 seems to be as follows:

DIP S2-4 ==> Input to large Lattice on TE0703 baseboard ==> Output from large Lattice on TE0703 baseboard ==> To B2B connector ==> Input to tiny lattice (U26) on TE0715 ==> Output from tiny lattice (U26 pin17, MODE2_R) ==> Input to Zynq MIO4 pin

The only piece of information we are missing is _which_ B2B (JM connectors) pin is the one that controls the U26 pin17 MODE2_R signal? Once we know this we can modify our custom board to add our own DIP switch that can control whether QSPI or SD card is selected for boot mode.

Thanks
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Trenz Electronic FPGA Modules / Re: TE0715 Mode2 (MIO4) signal (which B2B pin?)
« Last post by jwdonal on November 14, 2018, 11:37:50 PM »
After more research it appears that the MIO4 (MODE2_R) signal is driven by the tiny lattice on the module itself.

So how is this MODE2_R signal dynamically controlled from the TE0703 baseboard DIP switch S2-4?

We need to be able to select between SD and QSPI without using one of the Trenz baseboard and using our own custom board instead.
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Trenz Electronic FPGA Modules / TE0715 Mode2 (MIO4) signal (which B2B pin?)
« Last post by jwdonal on November 14, 2018, 11:18:06 PM »
Hello,

We are using the TE0715 module on our own custom board. This means that we do not have the Lattice chip that is typically included on, for example, the TE0703 baseboard.

We have just now realized that the Zynq MIO4 (MODE2_R signal on TE0715 schematic) signal which selects between QSPI or SD boot is normally driven by the lattice FPGA (pin17) on the baseboard. Since we do not have the Lattice on our custom board we need to know which B2B connector pin number on the TE0715 module to drive from our custom board in order to switch the MIO4 (MODE2_R) signal to 1 or 0.

We are unable to find any documentation on the schematics, the website, or the master pinout spreadsheet as to which B2B pin is attached to MIO4 (MODE2_R).

We know that this signal is routed through the B2B connectors since the lattice normally drives this signal.

Which B2B pin on the TE0715 is connected to the Zynq MIO4 (MODE2_R) signal?
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UltraScale / Re: PLL clock generators (Module and Board)
« Last post by ziladdev on November 14, 2018, 02:54:58 PM »
JH, thanks for the answer.

1) Could you please confirm that the TE803 SI is the same as the one on the carrier board, i.e. both have 0x70 as adress.
2) Please confirm that Table 20 (Carrier board TRM), Second part, I2C Switch position 4, corresponds to Si5388 on TE803 as the table mentions only the TE808 modules which seem to have Si5345.

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Trenz Electronic FPGA Modules / Re: ArduZynq: how much does it heat?
« Last post by sonycman on November 14, 2018, 02:49:12 PM »
So not that much of current, I see.
Think I should give that board a try.

Thanks!
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UltraScale / Re: PLL clock generators (Module and Board)
« Last post by JH on November 14, 2018, 02:28:41 PM »
Hi,

you must configure I2C switch at first, on the reference design it's done with our modified FSBL, also SI configuration (template included):

Both I2C switches are also included into the device tree of petalinux:
so bus can be selected directly, for example: i2cdetect -y -r 0, i2cdetect -y -r 1 i2cdetect -y -r 2 .... (enumeration depends on linux and connected I2C) 0 is basic I2C0 controller from zynq 1 is I2C1 controller from zynq, when activated or first mux output from the I2C mux with the lower address and so one.



https://wiki.trenz-electronic.de/display/PD/Si5338
--> There is a note on this pages, that SI has changed tools for SI5338 (we recognized this for some weeks). At the moment we provide only the template project for theClockBuilder Desktop but we will update step by step to clock builder pro.

br
John
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Trenz Electronic FPGA Modules / Re: ArduZynq: how much does it heat?
« Last post by JH on November 14, 2018, 02:13:20 PM »
Hi,
sorry that depends mainly on your design and cooling solution. you find the information, what the power regulator max. provide here:
And you can estimate power consumption with or use vivado from your project:

This board from last post with uboot+ some VIO on PL running appr. 1.1W at 5V USB after power on.

br
John
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