Author Topic: TE0712 with differential clock reference  (Read 489 times)

DG

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TE0712 with differential clock reference
« on: January 11, 2019, 08:56:39 AM »

Hi John,

we would like to supply a differential LVDS signal to the Si5338 on the TE0712 board.
Our purpose is, to lock the TE0712 to an external 10MHz signal reference. Since this frequency is a little bit low,
the onboard MMCMs of the FPGA are not able to generate any desired freqency. Therefore we want to use the Si5338.

The datasheet of the Si5338 states that ac coupling is required in addition to the termination resistor of 100R.

How can the termination at the end of the differential signal lines be achieved? Since you provide the possibility to
access the Si5338 with differential lines, how would you terminate the line and where should we place the ac coupling?

Thank you for your help in advance!
Kind regards,
Dino

JH

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Re: TE0712 with differential clock reference
« Reply #1 on: January 11, 2019, 11:44:41 AM »
Hi,
SI is preprogrammed, also with differential CLKs:
We use them on our reference design. You can also route MGT Refclk into FPGA Fabric(see also reference design):
Design contains also way to reprogram SI on power up.
In general for LVDS you can also activate Termination on IO Buffer, see:
Please check also our Note and links to 7Series LVDS on 7 Series Devices: https://wiki.trenz-electronic.de/display/PD/FAQ

br
John

DG

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Re: TE0712 with differential clock reference
« Reply #2 on: January 11, 2019, 12:24:17 PM »
Hi John,

thank you for your reply.
I have to describe our issue a little bit more in detail:

We want to supply a differential reference signal to the Si5338 via the signals CLKIN2_P/N and JM3 on the TE0712.
Since this signal is differential and in our case LVDS, we need a termination at the end of the line, i.e. between Pin 1 and 2 of the Si5338, U2.
In addition, as the datasheet states, we need ac coupling to the pins. How can this achieved with the TE0712?

You mentioned that the Si5338 is preprogrammed: is it preprogrammed to use CLKIN2_P/N too?

Which possibilities do you see to lock the Si5338 to an external signal reference, alternatively?

Kind regards,
Dino

JH

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Re: TE0712 with differential clock reference
« Reply #3 on: January 11, 2019, 02:21:10 PM »
Hi,

to you first post (sorry I read not correctly):
Quote
Our purpose is, to lock the TE0712 to an external 10MHz signal reference. Since this frequency is a little bit low,
the onboard MMCMs of the FPGA are not able to generate any desired freqency. Therefore we want to use the Si5338.
You can use simple CLK divider to reduce the output of an MMCM or check CLK buffer, like bufr:

To your new question:

SI5338 is preprogrammed to use onboard 25MHz and generated CLKs, which are described in the TE0712 TRM. How you can create other output CLKs is shown in the reference design also.

In case you want to connect external CLK, you must AC couple and terminate on the carrier. B2B IOs are connected directly to SI, see schematics:
br
John

DG

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Re: TE0712 with differential clock reference
« Reply #4 on: January 11, 2019, 02:34:19 PM »
Okay John,

Quote
In case you want to connect external CLK, you must AC couple and terminate on the carrier.

This is what I wanted to know (but I did not want to hear! :-[).

Thank you very much!

Kind regards,
Dino