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TE0720 Pull-up voltage for system-controller pins

Started by AndyH, December 07, 2018, 09:52:39 PM

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AndyH

Hello,

We are designing a custom carrier board for the TE0720, and I wanted to clear up what seems like an ambiguity in the TRM (https://wiki.trenz-electronic.de/display/PD/TE0720+TRM). It says:

QuoteIt is important that all carrier board I/Os are 3-stated at power-on until System Controller CPLD sets PGOOD signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10 and 12, meaning that all on-module voltages have become stable and module is properly powered up.

Does that apply to any of the carrier board I/Os that go to the system controller rather than to the Zynq? I'm specifically concerned with MODE, RESIN, and the three JTAG inputs (TDI, TCK, and TMS). I want to have pull-ups for all of these on the carrier board, but I have to choose between pulling them to (a) 3.3VIN, which we generate on the carrier board or (b) 3.3V, which comes BACK from the carrier board when the Zynq is powered up. (a) means the signal will be asserted earlier in the startup process, before the Zynq has power.

My instinct is that these signals should be pulled to 3.3VIN, because they go to a bank of the system controller (CPLD) that is powered by 3.3VIN.

JH

Hello,
this is refereed to FPGA IOs, see also Xilinx documentation:For JTAG, you should use JM2-91(JTAG VREF). In case of TE0720 it's the same like 3.3VIN, but we have also other 4x5 modules where it is connected directly to Xilinx FPGA and internal 3.3V is used.
Use the 3.3V or 1.8V output of the module to enable your power regulators of the FPGA IOs.   

So if the B2B IO is connected to 3.3VIN, you can pullup with 3.3VIN, if it's connected to internal  module voltage(3.3 or 1.8), you should use this one or your carrier voltage, which is enabled with 3.3V or 1.8V out.

We have some general notes to 4x5 power supply, controller IOs and general pinout:br
John