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TE0729 Gigabit Ethernet not working

Started by fhirschberg, November 30, 2018, 11:00:18 AM

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fhirschberg

Hi,

I'm using a TE0729 Zynq Board and have big trouble getting gigabit ethernet working.

Short description:

Build System is ptxdist
Using Kernel xilinx-xlnx current master
Xilinx U-Boot  (v2018.2)
An FPGA design derived from the example project of the board
Booting from SD card an FIT image containing DTB, Kernel and Initramfs

Whats working so far?
Everything I need! Except Gigabit Etnernet.

The MAC is detected fine. Also the PHY is detected.
Everything seems to work as expected, until you try using the gigabit lan.
When configuring the Interface and try to ping my developement host, i alyway got

macb e000b000.ethernet eth0: link up (1000/Full)
macb e000b000.ethernet eth0: link down

Repeating every 2 seconds...

No Packet is ever leaving the interface....

What i've done so far:

Tried the original SD card booting my image without success
Already tested older kernel versions like v2017.4 to v2017.1 without success

I'm out of ideas what i can do to get the ethernet working....
The other 2 ethernet-lite ports are working well!

When using the trenz demo sd card, all ports are working.


My Devicetree looks like this at the gem0 part:


&gem0 {
   status = "okay";
   phy-mode = "rgmii-id";
   local-mac-address = [00 0a 35 00 1e 53];
        xlnx,ptp-enet-clock = <0x69f6bcb>;
        enet-reset = <&gpio0 0x33 0x0>;
        phy-handle = <&phy0>;

   phy0: phy@0 {
      compatible = "marvell,88e1510";
      device_type = "ethernet-phy";
      reg = <0x0>;
      //marvell,reg-init = <0x3 0x10 0xff00 0x1e 0x3 0x11 0xfff0 0xa>;
   };

};


Maybe anyone can help? I'm out of ideas for now....

Thanks,
Florian

JH

Hi,
we have an 2018.2 reference design with wiki description,  prebuilt files and source code online:

ETH0 works with udhcpc and the other both must be configured manually, see reference design description.
br
John

fhirschberg

Thanks for your answer!

I know the reference design. And its working here without problems. Even gigabit lan is working.
But we are using ptxdist as a build system, not petalinux.
So i created a ptxdist project, downloaded kernel and u-boot from xilinx and put all together.
And i got everything working so far. Except the gigabit lan.
Our FPGA design is derived directly from the reference design and works prefectly, except gigabit lan... :-(

The IRQ for the Phy is not used in the reference design. Its polled there.
I already tried to assign the IRQ in our devictree, but that does not help...
I can't see any IRQs in /proc/interrupts from the phy when doing this. And in the reference design it works without it.

Does anyone has an idea what can cause the repeating link up/down messages, or has any hints getting closer to a solution?

Thanks,
Florian

JH

Hi,
problem is,  device tree and so one depends sometimes on the Xilinx version, which is used.
Xilinx petalinux 2018.2 used tag xlnx_rebase_v4.14_2018.2:

You can find our device tree changes on our wiki, and if you create one time the project also the automatically generated parts.
Or you extract device tree from image.ub and translate back to readable dts file.


If the links goes "up and down", I would say there is a loose contact, but when the reference design works fine, than it must be some other reason.

I never tried out ptxdist, so I can't really help there.  I can't also find much links in content with ptxdist on Xilinx Zynq, so I think you must try out or switch to other build environment.
Or ask on Xilinx forum, maybe the change is higher that somebody can help there.

br
John

fhirschberg

Hi John,

Thanks again for your answer.

QuoteOr you extract device tree from image.ub and translate back to readable dts file.

Already done that before, but looked a bit closer this time....

And at least i got it working....
Had some pinctrl configurations in devicetree that disturbed the MDIO bus somehow. Removed them, and everything works now!!!

Thanks for pointing in the right direction!

Florian