Author Topic: Information about how to use ZYNQ Design without using A9 Cores  (Read 84 times)

ZYNQ_STYLE

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Information about how to use ZYNQ Design without using A9 Cores
« on: November 09, 2018, 02:57:01 PM »
Hello community,

I hope you can help me concerning a post in "Trenz Electronic Wiki>Trenz Electronic Documentation>Application Note" with the title "ZYNQ Design not using A9 Cores".

The link to that specific post can be found here: https://wiki.trenz-electronic.de/display/PD/ZYNQ+Design+not+using+A9+Cores

Is there any possibility to get more information about how the block design has been created regarding the block "STARTUPE2 Primitive Wrapper"?

I couldn't quite comprehend how to create this specific block "STARTUPE2 Primitive Wrapper" since the underlying primitive in use (STARTUPE2) is not visible or being described the way it's being used.

Besides that, are there some more settings to be adjusted in order to get this design working?

It would be very kind if you helped me out, since that post had the best answer I could find for solving my problem (if it were described more thoroughly).

Greetings

JH

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Re: Information about how to use ZYNQ Design without using A9 Cores
« Reply #1 on: November 12, 2018, 12:11:21 PM »
Hello,

startup primitive is only a possible way to use the internal configuration clk, instead of external or PS-PL CLKs of the Zynq.
This IP contains only the Xilinx primitive, to make it accessible on the block design. Xilinx primitive hdl instance:
If this primitive is used by another IP, you must use the CLK from this IP.

This config clk is no very accurate and around 65MHz.

If you use PL only, than only JTAG is possible for configuration.

Easier is to generate a design with PS (use our board parts for correct initialisation) enabled, configure PS-PL CLKs like you need and then create FSBL and write Boot.bin with this configuration. Configure QSPI Flash with this Boot.bin and as long as you did not change the CLKs, you can use this on your design and configure PL part with your new design modification over JTAG after system is powered up(with boot mode QSPI).

br
John   


ZYNQ_STYLE

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Re: Information about how to use ZYNQ Design without using A9 Cores
« Reply #2 on: November 12, 2018, 04:32:13 PM »
Hello John,

first of all, I'd like to warmly thank you very much for your fast reply on my post. I really appreciate it.

That's exactly what I wanted: using the internal configuration clk (around 65 MHz) with PL only, because I'm using JTAG for configuration purposes.

I would like to avoid generating a design with PS (even though I have Trenz' board parts for appropriate initialization) owing to only using PL. These alternative (and more reasonable) steps, including configuration of PS-PL CLKs, creating FSBL and writing Boot-bin, etc. are clear to me.

Out of curiosity I wanted to program the PL portion straightforwardly onto the chip, using the inaccurate 65 MHz config clk, not even using the FSBL to achieve my goal. That's what I thought my referenced blog post "ZYNQ Design not using A9 Cores" was going to tell me.

But since I didn't know how the custom made "STARTUPE2 Primitive Wrapper (Pre-Production)" by Antti Lukats was internally wired and which ports of the primitive have been configured in what way, I hoped I could get an answer on how to create the same "STARTUPE2 Primitive Wrapper (Pre-Production)".

In general, is it possible to get PL to work on my board (TE0720 - Zynq SoC) without having to use FSBL? Also this answer would help me a lot.

Thanks for your time and I'm curious about your further help on that.

Cheers!

JH

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Re: Information about how to use ZYNQ Design without using A9 Cores
« Reply #3 on: November 13, 2018, 09:02:26 AM »
Hi,
you can download this ip in appr. one hour on:
--> PRIM_STARTUP.zip

it works also for other Xilinx versions.

But normally there is not to much to do, if you want to create your own IP:
and use startup primitive instance in this ip

"
In general, is it possible to get PL to work on my board (TE0720 - Zynq SoC) without having to use FSBL? Also this answer would help me a lot.
"
You can configure your system also over SDK XDC console and xilinx generated init scripts. But I don't understand way you do not want to generate the FSBL.
If you want to use PL only, it's much easer to use a purer FPGA, we have also Artix and Kintex FPG Modules on our 4x5 series. Zynq has no advantage compared to FPGA, if you use PL only.

br
John

ZYNQ_STYLE

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Re: Information about how to use ZYNQ Design without using A9 Cores
« Reply #4 on: November 13, 2018, 04:26:01 PM »
Hello John,

again, I must thank you for your keen answers and in general your extremely fast replies.

You have now helped me thoroughly, there are no further questions to pose from my point of view.  :)

On that note, once more: cheers!