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Display MAC address during FSBL of TE015-04-30-1C

Started by DavidAtAveillant, October 25, 2018, 10:12:21 PM

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DavidAtAveillant

I have been developing using a couple TE0720 modules, so have see all the additions made for reading and displaying the MAC address during FSBL.
However, I do not see the equivalent te_fsbl_hooks.c in the TE0715 module sw_lib directory.
Is this particular bit of code 'portable' between the modules, or do I need some extra information from you for this ?
TE0720 modules are te0720-03-1cfa or te0720-03-1cr;
TE0715 module is te0715-04-30-1c
(I am not using Petalinux, so I need to know how to make this work for baremetal/ucos operation)

Oleksandr Kiyenko

Hello,

TE0720 and TE0715 have a different interface to MAC information. To get MAC at TE0715 you need to read 24AA025E48T chip using I2C address 0x50. Registers from address 0xFA store unique EUI-48 address.

http://www.mouser.com/datasheet/2/268/20002124E-254617.pdf

Best regards
Oleksandr Kiyenko

JH

Hi,
at the moment read MAC from EEPROM i's only implemented on TE0720 with our own code on FSBL and UBOOT (both must be change to get our current solution running). It seems Xilinx has start EEPROM MAC reading with Vivado/Petalinux 2018.2 (check default platform-top.h), but we did not tested this new way from Xilinx at the moment, it's on our todo. If Xilinx way works fine, we will add this feature on the next updates.

br
John

DavidAtAveillant

I forgot to add - it would be useful if Trenz could update the 'MAC Address usage' page to clarify that it is *not* a standard option for the FSBL to display the stored MAC address on the primary UART. This only applies to a few modules (maybe only TE0720 ?), certainly not all.
https://wiki.trenz-electronic.de/display/PD/MAC+Address+usage

But many thanks for the clarification above.

JH

Hi,
this application note was last updated at 2015.  I think TE0720 was the first Zynq module from Trenz on this time.  But I will change this page a little bit to make it clearer, that this is not the default way for all modules.
Thanks to pointing that out.

br
John

DavidAtAveillant

John, very impressed with the swift response - many thanks !!

I'm going to look into what Xilinx provide in 2018.2, and will let you know if it helps (and if it doesn't  :) )