create project gui mode fails for TTEBF0808 Starterkit 2018.2

[ziladdev]

We recently moved away from 2017.4 to Vivado 2018.2. When I tried to re-run the starterkit scripts
./vivado_create_project_guimode.sh

I get an error in Vivado 2018.2 when generating the project:

----- VIVADO TCL CONSOLE

Start import design
INFO: [TE_UTIL-8] Following xdc files were found:
   /home/atl/dev/boards/trenz/2018.2/test_board/constraints/_i_bitgen.xdc
 /home/atl/dev/boards/trenz/2018.2/test_board/constraints/vivado_target.xdc
  ------
Set processing order normal for /home/atl/dev/boards/trenz/2018.2/test_board/constraints/_i_bitgen.xdc
Set use for implementation only for /home/atl/dev/boards/trenz/2018.2/test_board/constraints/_i_bitgen.xdc
Set processing order normal for /home/atl/dev/boards/trenz/2018.2/test_board/constraints/vivado_target.xdc
Set use for synthesis and implementation for /home/atl/dev/boards/trenz/2018.2/test_board/constraints/vivado_target.xdc
INFO: [TE_UTIL-2] Following block designs were found:
   /home/atl/dev/boards/trenz/2018.2/test_board/block_design/zusys_bd.tcl
  ------
INFO: [TE_INIT-8] Found BD-Design:
  TE::BD_TCLNAME:       zusys_bd
  TE::PR_TOPLEVELNAME: zusys_wrapper
  ------
  TE::IS_ZUSYS:        true
INFO: [TE_UTIL-2] Following block designs were found:
   /home/atl/dev/boards/trenz/2018.2/test_board/block_design/zusys_bd.tcl
  ------
INFO: [TE_BD-0] This block design tcl-file was generate with Trenz Electronic GmbH Board Part:trenz.biz:te0808_6eg_1e:part0:3.0, FPGA: xczu6eg-ffvc900-1-e at 2018-07-11T10:41:44.
INFO: [TE_BD-1] This block design tcl-file was modified by TE-Scripts. Modifications are labelled with comment tag  # #TE_MOD# on the Block-Design tcl-file.
INFO: [BD_TCL-3] Currently there is no design <zusys> in project, so creating one...
Wrote  : </home/atl/dev/boards/trenz/2018.2/test_board/vivado/test_board.srcs/sources_1/bd/zusys/zusys.bd>
INFO: [BD_TCL-4] Making design <zusys> as current_bd_design.
INFO: [BD_TCL-5] Currently the variable <design_name> is equal to "zusys".
INFO: [BD_TCL-6] Checking if the following IPs exist in the project's IP catalog: 
xilinx.com:ip:zynq_ultra_ps_e:3.2  .
INFO: [PSU-1]  DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change
Wrote  : </home/atl/dev/boards/trenz/2018.2/test_board/vivado/test_board.srcs/sources_1/bd/zusys/zusys.bd>
Wrote  : </home/atl/dev/boards/trenz/2018.2/test_board/vivado/test_board.srcs/sources_1/bd/zusys/ui/bd_ec7575b2.ui>
Adding cell -- xilinx.com:ip:zynq_ultra_ps_e:3.2 - zynq_ultra_ps_e_0
Successfully read diagram <zusys> from BD file </home/atl/dev/boards/trenz/2018.2/test_board/vivado/test_board.srcs/sources_1/bd/zusys/zusys.bd>
ERROR: [BD 41-758] The following clock pins are not connected to a valid clock source:
/zynq_ultra_ps_e_0/dp_s_axis_audio_clk

ERROR: [TE_INIT-146] Script (TE::VIV::import_design) failed: ERROR: [Common 17-39] 'validate_bd_design' failed due to earlier errors.
.
ERROR: (TE_INIT-146) Script (TE::VIV::import_design) failed: ERROR: [Common 17-39] 'validate_bd_design' failed due to earlier errors.
.
ERROR:(TE) Script (TE::INIT::run_project) failed: .
ERROR:(TE) Script (TE::main) failed: .
update_compile_order -fileset sources_1

[JH]

Hi,
select board part with the even ID, otherwhise only minimal configuration for custom carrier is used.
See:
https://wiki.trenz-electronic.de/display/PD/TE0808+StarterKit#TE0808StarterKit-DesignFlow
Step 4:Use Board Part Files, which ends with *_tebf0808

In your case select "26" for TE0808-04-06EG-1EE with TEBF0808 --> on design_basic_settings.cmd file: @set PARTNUMBER=26

br
John

[ziladdev]

Hi John.

It seems I used the wrong zip file. 

TE0803-test_board_noprebuilt-vivado_2018.2-build_02_20180814103119.zip (FAILED)
TE0803-Starterkit_noprebuilt-vivado_2018.2-build_02_20180814103221.zip  (OK)

I should perhaps open a new topic for this:
 Our design was initially developped on a Xilinx ZCU102 (ZU9), and the project consists of porting that design to a ZU3, thus our choice for a Trenz board + ZU3 MPSoC module.
In the vivado project, generated by Trenz scripts, there are several IP cores, in particular TEBF0808 Base Control and RGPIO IPs.
- What is the use of these? Sorry but the documentation is not really saying much.
- Are these necessary to the proper operation of the Carrier board?

Thanks for your reply.

[JH]

Hi,
TE0803-test_board_noprebuilt-vivado_2018.2-build_02_20180814103119.zip is the design for minimum configuration and the board part files without tebf0808 --> odd ID:

• https://wiki.trenz-electronic.de/display/PD/TE0803+Test+Board#TE0803TestBoard-DesignFlow

it's the same like in TE0808 for Starterkit use even:

• https://wiki.trenz-electronic.de/display/PD/TE0803+StarterKit#TE0803StarterKit-DesignFlow

Testboard is only with minimal periphery (QSPI and DDR and UART), all other MIO depends on carrier (UART also, but without UART, no output...).
RGPIO is simple serial interface between CPLDs and FPGA and SC is only IO wrapper:

• https://wiki.trenz-electronic.de/display/PD/TE0803+StarterKit#TE0803StarterKit-VivadoHardwareManager
• https://wiki.trenz-electronic.de/display/PD/RGPIO

Source Code is included into the project:

• https://wiki.trenz-electronic.de/display/PD/TE0803+StarterKit#TE0803StarterKit-DesignSources

Audio example does currently not work with 2018.2 petalinux, it's on todo to check changes and getting running again. It will be come on the fueature list, if we get it running again.

• https://wiki.trenz-electronic.de/display/PD/TE0803+StarterKit#TE0803StarterKit-KeyFeatures

br
John

[ziladdev]

Thanks John, really helpful.

We have finally decided to use the TE0803-02-04EV-1E3 MPSoC module with 4GB DDR4, However, after installing the board files, I see that the ZU4 baord files are only for 2GB DDR. Did I miss anything? Are there any specific settings to enable the whole 4GB?
 

[JH]

Hi,
i've update design files on Friday, TE0803-02-04EV-1E3 is now included

• https://wiki.trenz-electronic.de/display/PD/TE0803+StarterKit#TE0803StarterKit-Hardware
• https://wiki.trenz-electronic.de/display/PD/TE0803+StarterKit#TE0803StarterKit-RevisionHistory

Can you download again please.
br
John

[ziladdev]

Thanks JH,

I have downloaded the latest release and indeed I can now see the 4GB variant.
So that's solved!

Based on this board file, I ve done a very simple baremetal hello world test design (basically just the MPSoC) syntehsized and exported.
When I run the hello world SDK program I end up with a pop-up error nessage and the following SDK log:

>> SDK LOG

08:57:59 INFO   : Connected to target on host '127.0.0.1' and port '3121'.
08:57:59 INFO   : 'targets -set -filter {jtag_cable_name =~ "JTAG-ONB4 25163300133CA" && level==0} -index 0' command is executed.
08:58:10 INFO   : FPGA configured successfully with bitstream "/home/atl/dev/designs/project_me2/project_me2.sdk/main_wrapper_hw_platform_0/main_wrapper.bit"
08:58:16 INFO   : Connected to target on host '127.0.0.1' and port '3121'.
08:58:16 INFO   : Jtag cable 'JTAG-ONB4 25163300133CA' is selected.
08:58:16 INFO   : 'jtag frequency' command is executed.
08:58:16 INFO   : Sourcing of '/opt/Xilinx/SDK/2018.2/scripts/sdk/util/zynqmp_utils.tcl' is done.
08:58:16 INFO   : Context for 'APU' is selected.
08:58:17 INFO   : System reset is completed.
08:58:20 INFO   : 'after 3000' command is executed.
08:58:20 INFO   : 'targets -set -filter {jtag_cable_name =~ "JTAG-ONB4 25163300133CA" && level==0} -index 0' command is executed.
08:58:31 INFO   : FPGA configured successfully with bitstream "/home/atl/dev/designs/project_me2/project_me2.sdk/main_wrapper_hw_platform_0/main_wrapper.bit"
08:58:31 INFO   : Context for 'APU' is selected.
08:58:31 INFO   : Hardware design information is loaded from '/home/atl/dev/designs/project_me2/project_me2.sdk/main_wrapper_hw_platform_0/system.hdf'.
08:58:31 INFO   : 'configparams force-mem-access 1' command is executed.
08:58:31 INFO   : Context for 'APU' is selected.
08:58:31 INFO   : Sourcing of '/home/atl/dev/designs/project_me2/project_me2.sdk/main_wrapper_hw_platform_0/psu_init.tcl' is done.
08:58:32 ERROR   : Timeout Reached. Mask poll failed at ADDRESS: 0XFD4023E4 MASK: 0x00000010

08:58:32 INFO   : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source /opt/Xilinx/SDK/2018.2/scripts/sdk/util/zynqmp_utils.tcl
targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "JTAG-ONB4 25163300133CA"} -index 1
rst -system
after 3000
targets -set -filter {jtag_cable_name =~ "JTAG-ONB4 25163300133CA" && level==0} -index 0
fpga -file /home/atl/dev/designs/project_me2/project_me2.sdk/main_wrapper_hw_platform_0/main_wrapper.bit
targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "JTAG-ONB4 25163300133CA"} -index 1
loadhw -hw /home/atl/dev/designs/project_me2/project_me2.sdk/main_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x80000000 0xbfffffff} {0x400000000 0x5ffffffff} {0x1000000000 0x7fffffffff}]
configparams force-mem-access 1
targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "JTAG-ONB4 25163300133CA"} -index 1
source /home/atl/dev/designs/project_me2/project_me2.sdk/main_wrapper_hw_platform_0/psu_init.tcl
psu_init
----------------End of Script----------------

Any help on this is most welcome![/list]

[JH]

Hi,

there is a hello TE0803 prebuilt Boot.bin included. Try out please, put on SD and boot from  SD it's Hello TE0803 in endless loop.

• https://wiki.trenz-electronic.de/display/PD/TE0803+StarterKit#TE0803StarterKit-Launch

For SDK Debugger:

• Set Boot Mode to JTAG
• Disable Xilinx init script on debugger configuration, because init script will not initialise SI5338 and without SI5338  GTP Reference CLKs are missing. Xilinx init scripts check also GTP status and stops with faild. --> Disable GTP on PS(PCIe,DP,SATA,USB3) is also possible or -->   boot with reference Design Hello TE0803, change boot mode to JTAG and press reset (not power) , so SI is programmed and init script should work.

br
John