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CPLD Programming by Out-of-Box Vivado Project

Started by kjl, September 17, 2018, 09:46:52 PM

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kjl

Hi everyone,

        I going to summarize some info about how I came to this problem. So after successfully booting PetaLinux via SD on the TE0803 StarterKit using the hdf file exported from the Vivado project that was created using the provided scripts from Trenz, I wanted to try to boot PetaLinux from SD again with a new Vivado Project with just the Zynq Ultrascale+ SOC IP. However, upon realizing that nothing was showing through the UART, some digging around the schematics made it clear that the MIO assigned for UART0 (42 and 43 in this case) are wired to CPLD. So I am guessing the reason nothing is showing up (not even the FSBL) is due to the CPLD not being programmed. Hence, my question is this (split into a few parts):
1. How does the provided Vivado project (from the automated scripts by Trenz) manage to program the CPLD so that the UART is actually connected to the MIO?
2. If it is just using a default CPLD firmware, how does one go about to make sure that firmware gets loaded onto the CPLD?

I am sure I have a few errors or holes in my understanding as I am quite new so I really appreciate any comments or advice even if they do not directly answer my queries.

Thank you again everyone!

K.

kjl

Hey everyone,

          Just a small update. So I came upon this page: https://wiki.trenz-electronic.de/display/PD/TEBF0808+Slave+CPLD which says that MIO 42 and 43 are correctly connected to FPGA UART RX and TX; it is exactly the configuration I am after. I am guessing my own Vivado project did not configure which firmware (CPLD master or slave) and it just defaulted to master, when I want slave to run. So then my question becomes this:
What switch or button or software toggle is available to choose between the master and slave firmware for the CPLD on the TE0803 StarterKit?

Thanks again!

K.

JH

Hi,

CPLD is always programmed on power up. This has nothing todo with the Vivado design.

Did you set boot mode correctly (DIP stitch) for SD Boot?

In case you create your own project, use our board part files to get correct setup. There is one for TEBF0808 (TEBF0808 MIOs are set) and one for custom carrier (only QSPI, UART and DDR is set). You must use this for TEBF0808.
In case you use the board part files for tebf0808, you need also modified FSBL(SI5338 configuration). You can use default FSBL only, if you disable GTP interfaces on PS, which used SI5338 CLKs.

br
John

kjl

Hey John,

          Thanks for the insightful reply! Yup the DIP switch is set correctly for SD boot. I have two follow-up questions:
1. So we can only use the default TE modified FSBL if GTP interfaces on PS are disabled? Where can I find more information on the modified FSBL?
2. Regarding the master and slave CPLD firmware that is available on-board by default, when and what determines which firmware gets to run?

Thank you!

K.


JH

Hi,

Quote
1. So we can only use the default TE modified FSBL if GTP interfaces on PS are disabled? Where can I find more information on the modified FSBL?
Source code is also in the download, see all describtion:


Quote
2. Regarding the master and slave CPLD firmware that is available on-board by default, when and what determines which firmware gets to run?
Firmware is also available on the download area. Which version you has depends a little bit when you bough the carrier.

br
John