Trenz Electronic Products > UltraScale

PL Power Status OFF, cannot connect PL TAP

(1/4) > >>

gawrcool:
Hi,

I'm using Vivado 2018.2.1 64bits on Win10 system. I use TE0803-01-03EG-1EB on the UltraITX+ baseboard.
I use the TE0803-Starterkit-vivado_2018.2-build_02_20180814103204

The synthesis and implement process are successful. But when I use "Open Hardware Manager", I get the following:

[Labtools 27-3421] xczu3_0 PL Power Status OFF, cannot connect PL TAP.  Check POR_B signal.

I've searched over the web for this but nothing was relevant for me (in my opinion).
I've verified that the "design_basic_settings.cmd" is well modified for the board:
@set PARTNUMBER=8

Can you help me?

Regards,


 

gawrcool:
Solved, sorry, don't know how  ;D

JH:
Hi,
ok, good that it works again.
Which carrier did you use?
This message is independents from reference design. It's a new message since vivado 2018.1 or 2018.2 vivado read back some power control register from the ZynqMP, maybe PL part was not powered on --> PL part on can be disabled on the module.
There are also power save mechanism on ZynqMP itself possible.
See:

* https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdfpage 29 figure 1-2 Power Domains and Islands

br
John

gawrcool:
I use the TEBF0808-04
Thank you for the advice

JH:
Hi,
stand-alone? Did you use ATX power supply or external 12V. I think 12V only or?  If so, I think you has not powered on the module at the first time. In this case, module is not completely powered of, if you did not press the power button. CPLD Firmware was manly made for ATX power supply. On stand-alone usage it will be powered PS part at the moment --> PS has power, PL not.  I will try to develop a Firmware which will prevent this state, but I can't tell you a timeline at the moment.   
br
John

Navigation

[0] Message Index

[#] Next page