News:

Attention: For security reasons,please choose a user name *different* from your login name.
Also make sure to choose a secure password and change it regularly.

Main Menu

TE0720 and Power Sequencer

Started by joseph, August 28, 2018, 05:32:42 PM

Previous topic - Next topic

joseph

Dear All,

I have a question about the delay between the + 3.3v power supply applied to the TE0720 module and the PGOOD indicator.
> NOSEQ_pin at low level (normal mode)
> good power + 3.3v with low ripple.

Some information can be read on page 31/88 of the TE0702 User Manual but it is not clear.
If someone hangs out here, I'm interested







JH

Hi,

difference between NOSEQ high/low is only the enable of 1V and 1V8V:
In case of NOSEQ high, they will be enabled, if VIN is available (over SN74LVC1G97 (U21 and U25 on schematic)):
In case NOSEQ is low (CPLD check power):
CPLD controlls enable Pin:

       
  • ON_1V0, if EN1 is set(with small register delay (~25MHz internal CLK))
  • ON_1V8, if PG_1V0 and EN1_g is set(with small register delay (~25MHz internal CLK))
  • ON_1V5, if PG_1V0 and PG_1V8 and EN1_g is set(with small register delay (~25MHz internal CLK))
  • EN_3V3, if PG_1V0 and PG_1V8 and EN1_g is set(with small register delay (~25MHz internal CLK))
So in any case CPLD must be powered with 3.3V.
But I've no information about exact delay from 3.3VIN, VIN and power on of all regulators of the module.
PGOOD is low, if EN1 is low or the RESIN Pin.
In case you will supply Bank IOs, use the 3.3Vout or the 1.8Vout of the module to enable your bank power (for example with power switch). PGOOD is only monitoring and should not be used to enable Bank powers.
Some basics of the 4x5 modules:
br
John