Hi,
which reference design version did you use?
Xilinx has changed a lot between 2017.4 and 2018.1( or newer )
So there are many differences between xilinx git hub versions.
We only use petalinux (it's also Yocto based and has additional features), so I can't help so much.
Petalinux/SDK use also zynqmp-zcu102-revB as template and add changes during HDF import. We did not backup this changes, only changes, we must be add manually. See:
See especially device tree entry for ETH, maybe this is missing on your environment. We use also special FSBL (initialise SI5338). Xilinx FSBL, PMU and ATF(BL31) is not compatible during 2017.4 and newer version. So try to use all from the same version, also the correct Xilinx git hub version. We add FSBL templates to our project. For 2018.2 only: Remove compiler flags "-Os -flto -ffat-lto-objects" on 2018.2 SDK to generate FSBL.
To see default device tree after hdf import, you must create either petalinux project (we add a template into the reference design) or include the device tree git hub into SDK and generate default device tree. you must add device tree git hub, see "Generate a Device Tree Source (.dts/.dtsi) files from SDK" on
http://www.wiki.xilinx.com/Build+Device+Tree+BlobI hope this helps a little bit.
br
John