Starter Kit fails to build

[charlie5902]

Hi - I have TEBF0808-04A Carrier board and TE0803-01 module and Starter Kit downloaded and installed in Ubuntu 18.04.
The build scripts fail with the following tcl log:

Start import design
INFO: [TE_UTIL-8] Following xdc files were found:
   /home/charlie/Vivado/Starterkit/constraints/vivado_target.xdc
 /home/charlie/Vivado/Starterkit/constraints/_i_io.xdc
 /home/charlie/Vivado/Starterkit/constraints/_i_bitgen.xdc
  ------
Set processing order normal for /home/charlie/Vivado/Starterkit/constraints/vivado_target.xdc
Set use for synthesis and implementation for /home/charlie/Vivado/Starterkit/constraints/vivado_target.xdc
Set processing order normal for /home/charlie/Vivado/Starterkit/constraints/_i_io.xdc
Set use for implementation only for /home/charlie/Vivado/Starterkit/constraints/_i_io.xdc
Set processing order normal for /home/charlie/Vivado/Starterkit/constraints/_i_bitgen.xdc
Set use for implementation only for /home/charlie/Vivado/Starterkit/constraints/_i_bitgen.xdc
INFO: [TE_UTIL-2] Following block designs were found:
   /home/charlie/Vivado/Starterkit/block_design/zusys_bd.tcl
  ------
INFO: [TE_INIT-8] Found BD-Design:
  TE::BD_TCLNAME:       zusys_bd
  TE::PR_TOPLEVELNAME: zusys_wrapper
  ------
  TE::IS_ZUSYS:        true
INFO: [TE_UTIL-2] Following block designs were found:
   /home/charlie/Vivado/Starterkit/block_design/zusys_bd.tcl
  ------
INFO: [TE_BD-0] This block design tcl-file was generate with Trenz Electronic GmbH Board Part:trenz.biz:te0808_9eg_2i_tebf0808:part0:4.0, FPGA: xczu9eg-ffvc900-2-i at 2018-07-10T12:49:37.
INFO: [TE_BD-1] This block design tcl-file was modified by TE-Scripts. Modifications are labelled with comment tag  # #TE_MOD# on the Block-Design tcl-file.
INFO: [BD_TCL-3] Currently there is no design <zusys> in project, so creating one...
Wrote  : </home/charlie/Vivado/Starterkit/vivado/Starterkit.srcs/sources_1/bd/zusys/zusys.bd>
INFO: [BD_TCL-4] Making design <zusys> as current_bd_design.
INFO: [BD_TCL-5] Currently the variable <design_name> is equal to "zusys".
INFO: [BD_TCL-6] Checking if the following IPs exist in the project's IP catalog: 
trenz.biz:user:SC0808BF:1.0 trenz.biz:user:axis_live_audio:1.0 xilinx.com:ip:proc_sys_reset:5.0 xilinx.com:ip:vio:3.0 xilinx.com:ip:zynq_ultra_ps_e:3.2 trenz.local:user:RGPIO:1.0  .
WARNING: [BD 41-1306] The connection to interface pin /RGPIO/RGPIO_Master_CPLD/RGPIO_M_ENABLE is being overridden by the user. This pin will not be connected as a part of interface connection RGPIO_M_USR
WARNING: [BD 41-1306] The connection to interface pin /RGPIO/RGPIO_Master_CPLD/RGPIO_M_OUT is being overridden by the user. This pin will not be connected as a part of interface connection RGPIO_M_USR
WARNING: [BD 41-1306] The connection to interface pin /RGPIO/RGPIO_Master_CPLD/RGPIO_M_IN is being overridden by the user. This pin will not be connected as a part of interface connection RGPIO_M_USR
WARNING: [BD 41-1306] The connection to interface pin /RGPIO/RGPIO_Slave_CPLD/RGPIO_M_ENABLE is being overridden by the user. This pin will not be connected as a part of interface connection RGPIO_M_USR
WARNING: [BD 41-1306] The connection to interface pin /RGPIO/RGPIO_Slave_CPLD/RGPIO_M_OUT is being overridden by the user. This pin will not be connected as a part of interface connection RGPIO_M_USR
WARNING: [BD 41-1306] The connection to interface pin /RGPIO/RGPIO_Slave_CPLD/RGPIO_M_IN is being overridden by the user. This pin will not be connected as a part of interface connection RGPIO_M_USR
WARNING: [BD 41-1306] The connection to interface pin /RGPIO/RGPIO_Master_CPLD/RGPIO_M_RESET_N is being overridden by the user. This pin will not be connected as a part of interface connection RGPIO_M_USR
WARNING: [BD 41-1306] The connection to interface pin /RGPIO/RGPIO_Slave_CPLD/RGPIO_M_RESET_N is being overridden by the user. This pin will not be connected as a part of interface connection RGPIO_M_USR
WARNING: [BD 41-1306] The connection to interface pin /RGPIO/RGPIO_Master_CPLD/RGPIO_M_USRCLK is being overridden by the user. This pin will not be connected as a part of interface connection RGPIO_M_USR
WARNING: [BD 41-1306] The connection to interface pin /RGPIO/RGPIO_Slave_CPLD/RGPIO_M_USRCLK is being overridden by the user. This pin will not be connected as a part of interface connection RGPIO_M_USR
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
WARNING: [BD 5-232] No interface pins matched 'get_bd_intf_pins zynq_ultra_ps_e_0/S_AXIS_AUDIO'
ERROR: [BD 5-106] Arguments to the connect_bd_intf_net command cannot be empty.
ERROR: [Common 17-39] 'connect_bd_intf_net' failed due to earlier errors.
ERROR: [TE_INIT-146] Script (TE::VIV::import_design) failed: .
ERROR: (TE_INIT-146) Script (TE::VIV::import_design) failed: .
ERROR:(TE) Script (TE::INIT::run_project) failed: .
ERROR:(TE) Script (TE::main) failed: .
update_compile_order -fileset sources_1

Can you suggest a fix for this?

[charlie5902]

Actually technically the topic should read = Starter Kit Fails to create board design

[JH]

Hi,
which TE0803 assembly option do you have?

I think you have select the wrong board part files on the design_basic_settings.cmd file.
For TE0808/7/3 we offer 2 board part files, one for TEBF0808 carrier and one for custom carrier with other MIO settings. Both are included into the download.

Please select use the even ID from the csv file:

• https://wiki.trenz-electronic.de/display/PD/TE0803+StarterKit#TE0803StarterKit-DesignFlow

In case you has used product ID instead of ID (see /board_parts/TE0803_board_files.csv), than the first match is used (first one for custom boards) . So please select the even ID.
If you have still problems, let me know.

br
John

[charlie5902]

Ok I changed my board part selection from 7 to 8. Yes I had it wrong.
Tried to create project again after making the change and I still get the exact same errors.

Even though I had selected the wrong board part (which I did) - it still should have finished project creation, should have built, but failed to run on the board.
This was not the case.
The failure is in project creation when I run vivado_create_project_guimode.sh.
It does not complete populating the block design. There are unconnected ports and the design is not complete.
There is something wrong in the tcl scripts that create the project.

[JH]

Hi,

i use it with Win10 without problems. This missing connection normally only appears, if the wrong board part is included.

Can you send me the whole log file, if you run vivado_create_project_guimode.sh?
Location: Starterkit\v_log\vivado.log



Which Linux did you use?
Which Reference Design Version? TE0803-Starterkit_noprebuilt-vivado_2018.2-build_02_20180723204638.zip  or TE0803-Starterkit-vivado_2018.2-build_02_20180723204618.zip  or older one?

br
John

[JH]

Hi,

does it work now? Let me know, if you has still problems.

br
John

[charlie5902]

Hi - I see you have updated files for the reference designs in the download area. I will try these new ones and see if project creation succeeds.
I have been running by removing the offending items from the tcl scripts so I can get a basic project built.

Thanks,

Charlie

[JH]

Hi,
I add only new assembly variant on the last update:

• https://wiki.trenz-electronic.de/display/PD/TE0803+StarterKit#TE0803StarterKit-RevisionHistory

In case I should help, I need the vivado.vlog after  you run vivado_create_project_guimode.sh?
Location: Starterkit\v_log\vivado.log
You can send also to "support@trenz-electronic.de", if you do not want to post it in the forum.

br
John

[charlie5902]

Hi John,

thanks for your help so far.

I switched to trying the simple design download. It almost finishes block design creation but fails on unconnected clock input for audio.

Log is attached.

I am on Ubuntu 18.04 and Vivado 2018.2.

Thanks,

Charlie
 

[JH]

Hi,

for Test_board design use on odd ID, for starterkit design even ID on design_basic_settings.sh.
So for Testboard Reference Design and your TE0803-01-03EG-1E:
export PARTNUMBER=7
For Starterkit  Reference Design and your TE0803-01-03EG-1E:
export PARTNUMBER=8

See:
https://wiki.trenz-electronic.de/display/PD/TE0803+Test+Board#TE0803TestBoard-DesignFlow
-->Important: Use Board Part Files, which did not ends with *_tebf0808
https://wiki.trenz-electronic.de/display/PD/TE0803+StarterKit#TE0803StarterKit-DesignFlow
--> Important: Use Board Part Files, which ends with *_tebf0808

Test Board Design is only with Module components, so only QSPI, DDR and UART(UART this is normally also carrier depends)
https://wiki.trenz-electronic.de/display/PD/TE0803+Test+Board#TE0803TestBoard-PSInterfaces
Starterkit Design is with  Module und Carrier components
https://wiki.trenz-electronic.de/display/PD/TE0803+StarterKit#TE0803StarterKit-PSInterfaces

Test Board works with default FSBL, Starterkit Design only with modified FSBL, to initialize SI5345 for GTP CLKs (USB3, SATA, PCIe, DP).

br
John