TE0725-03-35-2C reset port in Vivado block diagram

[coloradosensors]

Hello,
I am using the XML board files for the TE0725-03-35-2C when I create a new Vivado project.
This creates an External Port called "reset" on my Block Design. The properties of this port indicate that it is active high.
The part0_pins.xml file shows the loc of this pin to be V10.

I look at the schematic of the board and expect to see a reset generator chip.

However, my schematic shows that V10 is connected to GND.

I am confused by this.

Is there an external reset circuit on the TE0725-03-35-2C?
Is it routed to an FPGA pin?
Is there a board file for such a configuration?

Cheers,
David

[JH]

Hello,

this is an "dummy" reset. So on power up (or rather on programming) it starts automatically the system. You can generate internal delay with FPGA logic if needed (or use Xilinx reset IP). Or use own components, connected to on of the free pins of the TE0720

br
John