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TE0712 ethernet communication

Started by Michael11, July 20, 2018, 02:02:54 PM

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Michael11

Hello,

I'm using a TE0712 FPGA board with the carrierboard T0703.
The Ethernet interface is used for communication between FPGA/Microblaze and a external PC.
After a larger changes at the FPGA this Ethernet communication is unstable. I have to restart the FPGA couple times until the Ethernet(UDP) communication starts up.
The confusing part is that the changes at the FPGA are not related to the Ethernet interface and after a successful start-up the FPGA works fine.  Has anyone discovered similar issues? I have already investigated the reset and startup of the eth phy on the T0703 but that looks ok.

Thanks in advance,
Michael

Oleksandr Kiyenko

Hello,
100M Ethernet communication usually working without any problems. Looks like you have unconstrained external ethernet signals and when your project gets bigger it becomes a problem.
Usually, these constraints are made by ethernet core. Please check
- if your project has no timing problems
- all Ethernet external pins have complete constraints set
- if you use external clocking, check if the clock has been properly defined

Best regards
Oleksandr Kiyenko