unable to load HelloWorld.elf file

[gingu]

I am using TE0803-01 board with Zynq part xczu4cg-sfvc784-1-e and 64-bit DDR4, 2GByte with part NT5AD256M16B2-GN. I am trying to create a simple project in Vivado and a HeeloWorld project in SDK. However, when I try to run the System Debugger I get the "Memory read error at 0xFD080030. Invalid DAP ACK value: 4" It seems to that my DDR configuration is wrong but I don't know why. Attached are:
1. my SDK log file "SDK.log"
2. my processor configuration "te0803..tcl"
2. my Vivado 2017.4 project board "te0803_bd.tcl"

[JH]

Hi,configs for NT5AD256M16B2-GN:

• CONFIG.PSU__DDRC__BG_ADDR_COUNT {1}
• CONFIG.PSU__DDRC__ROW_ADDR_COUNT {15}
• CONFIG.PSU__DDRC__DEVICE_CAPACITY {4096 MBits}
• CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits}
• CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2400R}
• CONFIG.PSU__DDRC__FGRM {4X}

We provide DDR configuration with out board part files. Thy are included into the reference design:

• https://wiki.trenz-electronic.de/display/PD/TE0803+Reference+Designs
• https://wiki.trenz-electronic.de/display/PD/Vivado+Board+Part+Flow

If you use board parts for TEBF0808, you must also use special FSBL with SI5338 initialisation, for MGT CLKS (USB3.0, PCIe, DP)

brJohn

[gingu]

Hello John,
Thanks for the message. The DDR settings were as you say, except the refresh rate was x1, now it is x4. Unfortunately I get the same error in SDK "Memory read error at 0xFD080030. Invalid DAP ACK value: 4" The following shows all my DDR settings and the attachment archive contains the board file te0803_bd_ddr_fgrm4.tcl (generated with write_bd_tcl). Please take a look, maybe I'm missing other settings, like, do I need to create any special Isolation for the DAP port?
   CONFIG.PSU_DDR_RAM_HIGHADDR {0xFFFFFFFF} \
   CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x800000000} \
   CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
   CONFIG.PSU__DDRC__BG_ADDR_COUNT {1} \
   CONFIG.PSU__DDRC__CL {16} \
   CONFIG.PSU__DDRC__CWL {12} \
   CONFIG.PSU__DDRC__DEVICE_CAPACITY {4096 MBits} \
   CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {1} \
   CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits} \
   CONFIG.PSU__DDRC__FGRM {4X} \
   CONFIG.PSU__DDRC__RANK_ADDR_COUNT {1} \
   CONFIG.PSU__DDRC__ROW_ADDR_COUNT {15} \
   CONFIG.PSU__DDRC__SB_TARGET {16-16-16} \
   CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2400R} \
   CONFIG.PSU__DDRC__T_FAW {30.0} \
   CONFIG.PSU__DDRC__T_RAS_MIN {32.0} \
   CONFIG.PSU__DDRC__T_RC {45.32} \
   CONFIG.PSU__DDRC__T_RCD {16} \
   CONFIG.PSU__DDRC__T_RP {16} \
   CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {1} \
   CONFIG.PSU__DDR__INTERFACE__FREQMHZ {600.000} \

Thank you,
Cristian Gingu

[JH]

Hi,

which carrier did you use?

br
John

[gingu]

Hi John,
The physical board I’m using is TE0803 https://shop.trenz-electronic.de/en/TE0803-01-04CG-1EA-MPSoC-Module-with-Xilinx-Zynq-UltraScale-ZU4CG-1E-2-GByte-DDR4-5.2-x-7.6-cm mounted on the carrier/test  board TET0808-01 https://shop.trenz-electronic.de/en/TEBT0808-01-Test-Board-for-TE0808-and-TE0803 which uses an FTDI JTAG adapter, Xilinx compatible  https://shop.trenz-electronic.de/en/TE0790-02-XMOD-FTDI-JTAG-Adapter-Xilinx-compatible.
I should add than I can program the FPGA with the bit file in both Vivado and SDK. My problem is downloading the elf (in SDK)
Thanks,
Cristian

[JH]

Hi,
can you try out:

• https://wiki.trenz-electronic.de/display/PD/TE0803+Test+Board
• https://wiki.trenz-electronic.de/display/PD/TE0803+Test+Board#TE0803TestBoard-Download

For TE0803-01-04CG-1EA you must select 21 on "design_basic_settings.cmd" --> you should see you selected device on the Vivado overview Window. Block Design is PS only.
For TET0808 also UART must be changed on PS IP (prebuilt uart is for other MIO on TEBF0808):

• https://wiki.trenz-electronic.de/display/PD/TE0803+Test+Board#TE0803TestBoard-Hardware
• open PS IP and select UART to "MIO68...69"

Create Bitfile and export HDF to SDK.Select new Application Hello Word and on the Hello world Project, right click  on the project and "debug as" Launch on Hardware.
Cyn you try out please.
br
John

[gingu]

Hi John,
I did what you say 1-2 weeks ago, that was my first try. However, I did it again  right now, using your zip archive build_09_20180517152103.zip. Changing all items as you suggest, part #21, UART 1 with MIO 68..69, keeping SPI feed back clock to MIO#6 although from board schematics page 11 this FPGA pin is not connected... then implement and export to SDK, create Hello World with both 32bit and 64bit and, unfortunately, both of them giving same error (memory read error at 0xFD080004. Invalid DAP ACK value 4).
So nothing new, nothing changed, same error.
Thanks,
Cristian

[JH]

Hi,

I did what you say 1-2 weeks ago,

? your first post is from June 18, now we have June 20? But OK.

SPI feed back clock to MIO#6 although from board schematics page 11

correct normally it's not needed, but since Xilinx changed MicroUboot with Vivado 2017.3, this must be enabled to get access to flash over Vivado/SDK (I found out this with one of our Zynq Board (ZynqBerry), I 've activated feedback CLK on all board part files without testing if it also needed on ZynqMP).

Can you tell me DIP switch settings from TEBT0808 and from the XMOD(TE0790) on the carrier?When you open JTAG with vivado, did you see the FPGA and ARM_DAP or FPGA and ARM_DUMMY?
br
John

[gingu]

The package content of the box I received say: 1xTEBT0808 and 1xTE0790-02. However, on the PCB I read TET0808-01.
The switches on TET0808 are:
S1=on+on+on+on (mode switches, all at ground),
S2=off+off+off+off (EN_PSGT, ENGT_R, EN_GT_L, EN_PLL_PWR, all at 3.3V) and
S3=off+off+off+off (EN_DDR, EN_LPD, EN_PL, EN_FPD, all at 3.3V)
The switches on XMOD TE0790-2 are: #1=on (JTAGEN=gnd), #2=off(DISEE=float), #3=off(VIO=float), #4=off(LDO_3V3=float
See also the attached photo.
I can see the FPGA and the ARM_DAP in Vivado, see attached file. I can program the bit file in Vivado
I can program the bit in SDK too:
15:31:24 INFO   : Connected to target on host '127.0.0.1' and port '3121'.
15:31:24 INFO   : 'targets -set -filter {jtag_cable_name =~ "JTAG-ONB4 25163300129EA" && level==0} -index 0' command is executed.
15:31:25 INFO   : FPGA configured successfully with bitstream "C:/Cristian/CodeLib/Trenz/TE0803/test_board_buid_09/vivado/test_board_buid_09.sdk/zusys_wrapper_hw_platform_0/zusys_wrapper.bit"

[gingu]

The TE0790 switches is attached here
Thanks,
Cristian

[JH]

Hi,

DIPs are OK for JTAG.

I've tried to reproduce it on my place, but here it works (I've another assembly version than you, but the steps are the same).

Can you tell me which external power supply you use? Is there a current limit?
Can you send me the serial number of your TE0803? You can send this number also to  "support@trenz-electronic.de" instead to write this here.


Can you try to start my application from flash. I put generated files on the attachment also a picture of the putty output.

• Set S1-2 to OFF S1-1, S1-3 and S1-4 on --> boot mode qspi
• power on
• open uart --> for example with putty. COM Port see device manager, speed 115200
• open Vivado HW manager
• Add Configuration memory device (right click on the fpga part (xzu3_0)). Memory is "mt25qu512-qspi-x8-dual_parallel" for your TE0803-01-4cg-1ea
• Select boot.bin and flash fsbl from the zip file
• Program and wait until it's finished (You should see FSBL output on the UART console)
• Reboot with the button from the XMOD (TE0790) (second FSBL output should appear and Hello TE0803 in endless loop)

Does this work? If not, can you tell me the Status of the ERR_OUT and ERR_STATUS and DONE LED (after reboot (step ).
PS:

• TET0808 and TEBT0808 is the same, this board was renamed only.
• You can configure FPGA with Bitfile also if the PS (ARM) has some problems. You need ARM initialisation to get access to flash or to activate PS-PL CLKs(from ZynqMP IP) for example.

br
John

[gingu]

Power Supply: Tektronix PW4602, Settings 3.3V with 1A compliance. Output 3.298V with ~.6A consumption.
The voltages measured on XMOD connector J2 are:J2-5(3V3) is 3.261V, J2-6(PS_1V8) is 1.798V
I should try to increase the power supply voltage until J2-5 goes up to 3.3? Right now on carrier TET0808 J8-J7 I have 3.27V, perhaps is too low?

Serial Numbers:
TE0803-01-04CG-1EA =>SN 508521
TEBT0808-01 => SN 511888

I'll try to start your application from flash. My previous attempts to program the flash were unsuccessful, see attached photo.

Thanks,
Cristian

[gingu]

Hi John,
I did follow your steps to program the flash, but it fails, see attached *.pdf file for more details.
I did a second attempt to program flash, it failed with similar results.
Additionally, I'm reporting the System Monitor voltages since I see that VCC_PSDDR_504 and VCC_PSINTFP are at zero volts.
I also increased my power supply output to 3.330V such as to measure 3.300V on carrier TET0808 J7-J8.
Thank you,
Cristian

[gingu]

BTW, talking about power supply, what type of banana or other connector will fit into J7-J8? Could not find something on my department part cabinets to properly fit into J7-J8.

[JH]

Hi,

it's 2,0mm MC LB2-A ( https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/5.2x7.6_Carriers/TEBT0808/REV01/Documents/SCH-TEBT0808-01.PDF -->page 2), so use  2mm banana plug.

1A is not enough. This Hello world need appr. 1A and during programming it can be higher.


VCCPSINTFP is only available on FPGA sysmon (XCZu4 sysmon).
VCC_PSDDR4_504 seems to be a feature, which is currently not supported by Xilinx (or never). It's also 0 on my running system
VCC_PSDDR4_504 is also not included in the sysmom documentation: https://www.xilinx.com/support/documentation/user_guides/ug580-ultrascale-sysmon.pdf


So at first please use a external power supply with 2 or 3 A.
PS: one think with can also happens is, that the hw_server.exe freeze, than everything can happens with JTAG. If you close Xilinx Software and hw_server.exe is still runing on Task Manager, please kill manually.

Let me know if this helps or not.

br
John


 

[gingu]

Hi John,

That was the key, now it's working, thank you. I set the current limit to 2A. The bare FPGA draws about 0.6A and when you program and run it goes to ~1.3A.

Now I was able, using your test_board_buid_09 and the BOOT.bin and zynqmp_fsbl_flash.elf you gave to me to do the following: program flash from Vivado; boot from flash the TE0803 board and see the message on a terminal; do my own Hello World elf file and lunch it from SDK.

I was also able, using my initial project, which dos not use any of your board files, to Launch on Hardware in SDK my own Hello World. This approach is important for us here at Fermilab because we intend to use your TE0803 (or similar) and our custom designed carrier boards for some High Energy Physics application to be used both at Fermilab (www.fnal.gov) and at CERN (www.cern.ch)

Thank you very much for your support and quick debugging. I should mention now that my similar case opened with Xilinx on June 11 is still not solved yet.

Finally, it would be nice if Xilinx Software would give a more "general" error type instead of the "specific" targeted error I received (DAP ACK error) in case the device is not powered properly. After all, with so many powering domains, configuration, monitoring, etc. it's a bit disappointing that such a trivial situation is not cached.

Thanks again,
Cristian 

[JH]

Hi,
nice to hear that it works now.

I was also able, using my initial project, which dos not use any of your board files, to Launch on Hardware in SDK my own Hello World

This is OK, to set DDR settings is the most important thing. Everything else is not quite so difficult. The most MIOs go to the B2B connector, so this configuration must be done by user, if he create an custom carrier.When you create your own carrier,  you should check your MIO connection with Vivado, to make sure, the you can set your MIO configuration.

Thank you very much for your support and quick debugging. I should mention now that my similar case opened with Xilinx on June 11 is still not solved yet.

Finally, it would be nice if Xilinx Software would give a more "general" error type instead of the "specific" targeted error I received (DAP ACK error) in case the device is not powered properly. After all, with so many powering domains, configuration, monitoring, etc. it's a bit disappointing that such a trivial situation is not cached.

This is not so easy, by the rebooting from the PCB power management, the state of all registers has changed and the software get other values as exacted. Many different reasons are possible for this kind of issue.
Some Notes for the future: There are also many mechanism on the ZynqMP, which can disable JTAG connection (especially if linux is running on ZynqMP). And sometimes  "hw_server.exe" freeze on the PC and you must kill them manually with task manager. This can happens for example if the JTAG connection will be interrupted without closing of the server.
ZynqMP is a configurable system, so it's nearly impossible for Xilinx  to catch all cases of possible issues for every possible configuration of the zynq.

Some Xilinx documents, which will be interesting for you:

• https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf
• https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers.html
• https://www.xilinx.com/support/documentation/user_guides/ug1137-zynq-ultrascale-mpsoc-swdev.pdf

We add also some links and additional notes on our wiki:

• https://wiki.trenz-electronic.de/pages/viewpage.action?pageId=14746264

br

John