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SDRAM Interface

Started by asc1, June 15, 2018, 04:12:17 PM

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CYC1000 comes with an SDRAM chip, but there is no SDRAM core in the Quartus IP library. According to the NIOS ref design it should be possible to use a NIOS based controller, however the ref design is incomplete (to my taste) and checking the pinout revelas that there is no clock for the SDRAM chip coming from the FPGA.
Please clarifiy how to properly use the SDRAM, preferable also without NIOS.
I use the CYC1000 for teaching and have some designs running on it, so the rest of the board is nice (few more switches would be good, though)


I got my CYC1000 last week, and found the same issue.

I fixed the reference NIOS design to work with on-board SDRAM:

Primary changes from the original design are as follows:

  • SDRAM related port directions (input or output) defined in the top module (top.v) are fixed.
  • A phase shifted PLL output and its output pin are added to provide a clock for SDRAM.
  • Sample Eclipse projects are included, which use SDRAM as a main memory.

Enjoy it ;)


Hi Minatsu,

  Thank you for sharing your design!
  Just cloned your design from github. Quick check shows that MEM_CLK pin is not assigned to the physical pin. This is excerpt from qsf file:
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MEM_CLK

  When checking pin planer pin B14 is shown as unsigned as well.


Hi microchaos,

Thank you for checking my design.

I am new at FPGA, and interested in fitter's automatic assignment ability because I found that PIN_B14 has "PLL2_CLKOUTp" function.
It seems that PLL2 is intended to be used as a clock generator for SDRAM on CYC1000.

I assigned a location of my_pll (pll0) to PLL2 by assignment editor, and leaved MEM_CLK unassigned.
Then I found that MEM_CLK is automatically assigned to PIN_B14 by fitter at compilation time.

However, of course it is better to assign MEM_CLK to PIN_B14 explicitly to avoid any unexpected behavior, so I updated my design on github.


Thank you for sharing the design! :-)
I noticed also that the SDRAM QSYS project did not provide a clock for the SDRAM. I found this design and am now wondering why the PLL is not designed in the QSYS/Platform Designer project?
And why 48MHz and not 166MHz?

Bear with me as I am new to Intel FPGAs and Quartus Prime. I ordered the CYC1000 and am still waiting to receive it and dabble with the projects while waiting.
However, I found the Intel online lectures to go over the IP and design very little detail on other than the tool.
For this reason, I am also wondering why both data and instruction master is routed into PIO in the original design. Any idea why instruction master need to be there? (I found it not to be so from the github design though)


Why isn't the speed faster?  The I/O is cabled of 200Mhz.

Thomas D

the maximum clock frequency for the sdram chip is 166Mhz. In the documentation of the sdram controller ip ( Intel says: "The clock for the SDRAM chip (SDRAM clock) must be driven at the same frequency as the clock for the Avalon® -MM interface on the SDRAM controller (controller clock)." So the maximum frequency you can choose for the sdram chip and the sdram controller is 166Mhz.

A reference design for cyc1000 with pll and sdram controller designed in platform designer is also available at In this example the frequency for the sdram chip and the sdram controller is 50Mhz. You also can change the frequency, but which frequency you choose is depending on your design.

Thomas Dück