How to add simple PL to TE0745 Basic Linux Example

[TrenZid]

I am an experienced FPGA developer (Virtex 7, Virtex 6), but I am new to Zync and the concept of PS vs PL logic.  I have a TE0745 on a TEB0745 carrier.  I can rebuild the Basic Linux Example in Vivado 2017.2 and load it to the FPGA over JTAG.  I would like to add some simple PL logic to toggle a bit on one of the headers as a simple first step to adding PL, but I can't figure out where to begin.  Let's say I want to toggle B12_IO0 which ties to fpga pin W14 at about 1Hz.  Do I edit zsys_wrapper.vhd?  How do I specify pinouts?  Actually, it looks like pinouts may already be specified for all the IO not used by the example, but I can't figure out where.  I feel like there should be a plethora of Xilinx and Trenz documents on how to proceed, but I can't find one to help me get started.

[Oleksandr Kiyenko]

Hello,

you can modify zsys_wrapper.vhd to add your logic, but this way is not recommended workflow, because of each time you modify block project Vivado will regenerate this file. The correct way to add your logic to
PL, is create and instantiate custom core. You can specify pinout in *.xdc file.
Xilinx provides a lot of training videos which can help you
https://www.xilinx.com/video/hardware/packaging-custom-ip-integrator.html
You can also use your code as RTL core. Just add your VHDL/Verilog file to project and then convert it to RTL core using menu option "Add module to block design"

Best regards
Oleksandr Kiyenko