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Issues with pin J1-A19 on TE0715+TE0703

Started by jwdonal, May 09, 2018, 12:30:39 AM

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jwdonal

Hello,

We are having an issue utilizing J1-A19 on the TE0703 base board with TE0715 module. We have discovered that if anything other than air is connected to this pin the FPGA module will not program/boot properly.

According to the schematics J1-A19 is a simple, non-special-purpose, FPGA GPIO pin (B13_L3_P). Is there anything unique about this signal or how it is routed on the base board or the FPGA module board? Is it routed close to any high speed signal that might result in some kind of capacitive coupling/interference/crosstalk?

We have a video of a test that we performed with J1-A19 that demonstrates the issue, however, the video is ~65MB which is more than the max file size limit allowed on this forum. Is there any way that we can get this video to you?

The video shows the TE0715+TE0703 boards booting properly when nothing is attached to J1-A19. We then touch a 10kOhm resistor to pin J1-A19 and the FPGA module does not boot at all. We have performed this test 30 times each and the problem is consistent.

- With no resistor touching J1-A19 the FPGA boots/loads successfully 30 out of 30 times.
- With 10kOhm resistor touching J1-A19 the FPGA does NOT boot/load successfully 30 out of 30 times.
- We have performed this same test on 4 separate pairs of TE0715+TE0703 boards. All pairs of boards behave identically.

We would like to get the video to you if at all possible.

Can you provide any information related to the layout/path of this signal on the board?

JH

Hello,

at the moment I can't reproduce this error on my place.
Can you please answer following question:
I will try to reproduce this issue again, when I get this information from you.
br
John

jwdonal

#2

       
  • Which Power supply unit did you use --> any current limit?
        We have tested with 3 different power supplies. One is a bench top power supply with current limit set to 4A (our running design has never exceeded 480mA). The other supplies are 2 standard commercial DC power bricks both rated for 5V @ 4A. The behavior was the same with all power supplies on all 4 sets of boards.
           All 4 FPGA module boards tested are TE0715-04-30-1I
   
  • Which TE0703 Revision did you use?
        All 4 base boards tested are Revision 05
           We have been using our same basic U-boot+Linux design that we have been using successfully over the last few months, but we can try yours if you think that will help track down the problem.
   
  • Which IO Bank voltage did you select?
        VCCIOA is set to 3.3V with VCCIOB-D set to 1.8V. Additionally, we are booting from the SD card, not the QSPI (i.e. S2 switch 4 in ON position).
   
  • Where did you connect the 10kOhm? J1-A19 and VDD or GND? Same VDD like IO bank power?
        In the resistor test case it was an axial lead resistor and we were simply holding the other end of it with our finger while touching the opposite end to J1-A19 (you can see this in the video if you want us to send it to you). We have actually tried several different things to see what would break it including but not limited to the following:

- Touching J1-A19 gently with our finger (in ESD safe lab with ESD garment and grounded with wrist strap)
- Touching J1-A19 with 10kOhm resistor (in ESD safe lab with ESD garment and grounded with wrist strap)
- Touching J1-A19 with a dissipative ESD bag (in ESD safe lab with ESD garment and grounded with wrist strap)
- Placing a standard ~0.5in header pin inside the J1-A19 hole (without touching it)

All of the above test cases cause the FPGA boot sequence to fail. We have been working on this for 2 full days. We have many more test cases but there is probably no point in listing all of them. We have many videos documenting the issue that we could send you if you think they will help. We've had several engineers looking at this over the past 2 days. It's a rather fascinating mystery, especially since the schematics indicate there is nothing at all special about this particular pin. If we had the layout files we could probably figure it out ourselves rather quickly but since we don't have them we must rely on you for help. You should also know that we have performed the same tests with all other (32x3) pins on the J1 connector and we are unable to cause the problem. This problem is absolutely specific to J1-A19. We have also seen no issues with any of the pins on J2.

We have been having tremendous success with these boards over the last few months using them standalone, however, just last Friday we started trying to use the J1/J2 connectors for our particular application and we stumbled onto this problem.

JH

Hi,

I said, I couldn't reproduce this issue at the moment, not that I didn't believe you.
Can you please try out the reference design one time, and let me know what's happens. I will try to get nearly the same setup on my place, that's the reason for my request.

br
John

jwdonal

I'm sorry, I'm confused...did I make any statement at all saying that you didn't believe me? I simply told you what we did and provided detailed answers to all of your questions and offered more information if you needed/wanted it. And I also said we were willing to try the reference design. Your response is very strange...what did I say that was wrong?

JH

 
Quote...not that I didn't believe you.
-> This mean: I believe that you has this issue.

Sorry for this confusion, my English is not the best.

I can't reproduce this at the moment, that's my problem.
br
John

JH

Hi,

is there any update? Do you have the same issue with the reference design?

br
John

jwdonal

Hello,

We've had several engineers working on this problem and following this thread so I'm not sure who tested the reference design. I believe the result was the same. But I can't say that with certainty.

However, I'm not sure that matters too much because we did figure out a solution that appears to solve the issue completely. The solution was to add a directive to our XDC file to tell Vivado to enable the internal weak pullup in the J1-A19 (B13_L3_P) IOB. We do not understand why this fixes the problem because, as I stated before, this pin is unused by our design. Additionally, Vivado user manual states that all unused IOBs are set to weak pull-down by default. It's possible Xilinx changed something recently with their tools such that this is no longer the case. Unfortunately we don't have any additional time to spend researching this problem.

In summary, this issue has been worked around by enabling the internal weak pull-up on J1-A19. Hopefully this information might be valuable to someone else in the future.

Regards