The Design Fail to Meet the Timing Requirement

[jinyu]

  Hi,
      When I use Vivado2017.1 run the Implementation of example that I use vivado_create_project_guimodegenerated in the folder  IIoT-EDDP\HLS\ARTY_Z7_FULL \vivado ，it replied  the following  critical warning message ： [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.and there are about 800 warning such as Type mismatch between connected pins   have a lot of unconnedted ports unused sequential element and so on. Although there is a critial warning,but it can generate the bitsteam successfully。
     can you give me some advice how to deal with my problems ?
     Before implemation,I didn't make any exchange of this example.
     the operation system is windows 10 professional build 16299，，and ， and it's  Not pirated
     I can make sure the version of vivado is vivado2017.1
     Is anyone can go though the Implemation successfully?any help will be appreciate.

best regards
     

[JH]

Hi,
we will check this. I let you know, when I find out something.
br
John

[jinyu]

Thank you very much~

best regards

[JH]

Hi,
change implementation strategy to: Performance_ExplorePostRoutePhyOpt.

Use GUI --> Implementation settings

or TCL script -> set_property strategy Performance_ExplorePostRoutePhysOpt [get_runs impl_1]

br
John

[jinyu]

thank for your reply, but still not go through the implementation ,because of the failed timing.

[JH]

Hi,

default project without modification?
I've try out with and without strategy changes, see attachment.
In my case impl1 is default and impl2 with new impl strategy.


br
John

[jinyu]

Hi，

I deleted all the project files and tried again,but still encountered such problem.

my proceed as follows ,please check it and give me some advice.

1.unzip IIoT-EDDP to a folder

2.navagate to IIoT-EDDP-master/IIoT-EDDP-master/HLS/ARTY_Z7_FULL

3. click _creat_win_steup.cmd

4.select 0 for min setup then it will generate some file in this folder.

5.run vivado_creat_project_guimode.cmd ,then vivado will start and generate the project automatically.

6.after the project build finished, then , I right click IMPLEMENTATION > implementation settings > set strategy:Performance_ExplorePostRoutePhysOpt

7.  Run Implementation > a dialogue box poped up notifing me there is no netlist avaiable ,then I Click ok > a Launch Run dialogue box pops up ,then  I check the box that Launch runs on local host  > OK

8. about twenty minutes later , it will notify me that there have a critical warning: [Timing 38-282] The design failed to meeting the timing requirements.

regards

[JH]

Hi,

can you send me the vivado.log file to support@trenz-electronic.de, from project creation up to bifile generation?
Location is ./v_log/vivado.log if you use our scripts.

At the moment i can't reproduce this, so it's hard to fix it.

Can you also send me the 3 failing endpoints from timing analysis?

br
John

[jinyu]

hi,John
   
  I upload the files you need, please check ....any help would be appreciated~


best regards

[JH]

Hi,

i found out my git download also failed (i've open to much vivado projects, so i didn't select the correct on the picture i've upload, sorry).
We have a newer version on or backup system. Not all Buttons are included, this this timing will pass. We will test project again before we update git hub,
but i add the files to the attachment.

   
•     replace "/block_designs/zsys_bd.tcl"  with this on on the attachment
•     replace "/constraints/Arty_Z7.xdc"  with this on on the attachment
•     put project_settings.tcl from the attachment into  /settings/ folder
•     Create the project again with the scripts --vivado_creat_project_guimode.cmd.

1. and 2. are the changes from design, 3 set design strategy automatically, 4 will create the project with the changes.


br

John

[jinyu]

Hi，

   You made it, It meet the timing requirement  thank you~

Though there are still some problems ,but I think it will be solved as soon as you update your repository.
   
   Occasional mistakes are unavoidable, wating for your git repository updated

regards

[JH]

Hi,

can you tell me which problem you has?

br
John

[jinyu]

 Hi,

     problems such as output delay is missing    mutiple clocks involved on source or destination of a bus skew constraint and  The FDPE cells is not placed in the same (SLICE) site . the detail message I have uploaded ,please check the attachments.

regards

[JH]

Hi,

not all warnings must be solved. Also output/input delay is not always necessary.  This depends on design, logic speed you would obtain....so some of them can be ignored.

br
John

[jinyu]

hi,

  You solved my problem. thank you very much , you're the greatest !

best regards