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TE0715 FCLK125 Signal

Started by jwdonal, March 25, 2018, 04:02:34 AM

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jwdonal

On the TE0715, why is the FCLK125 signal (generated by the SI5338) not connected to a clock-capable pin (e.g. SRCC/MRCC) on the FPGA?

JH

Hi,

this clk is optional and add to a free IO which was not used. All other SRCC/MRCC was used for other purpose.
You can add Vivado constrain to use it on clk net.

br
John