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The Design Fail to Meet the Timing Requirement

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jinyu:
  Hi,
      When I use Vivado2017.1 run the Implementation of example that I use vivado_create_project_guimodegenerated in the folder  IIoT-EDDP\HLS\ARTY_Z7_FULL \vivado ，it replied  the following  critical warning message ： [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.and there are about 800 warning such as Type mismatch between connected pins   have a lot of unconnedted ports unused sequential element and so on. Although there is a critial warning,but it can generate the bitsteam successfully。
     can you give me some advice how to deal with my problems ?
     Before implemation,I didn't make any exchange of this example.
     the operation system is windows 10 professional build 16299，，and ， and it's  Not pirated :P
     I can make sure the version of vivado is vivado2017.1
     Is anyone can go though the Implemation successfully?any help will be appreciate.

 best regards
     

JH:
Hi,
we will check this. I let you know, when I find out something.
br
John

jinyu:
Thank you very much~

best regards

JH:
Hi,
change implementation strategy to: Performance_ExplorePostRoutePhyOpt.

Use GUI --> Implementation settings

or TCL script -> set_property strategy Performance_ExplorePostRoutePhysOpt [get_runs impl_1]

br
John

jinyu:
thank for your reply, but still not go through the implementation ,because of the failed timing.

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