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TE0715 QSPI special FSBL

Started by jwdonal, March 22, 2018, 06:26:08 PM

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jwdonal

https://wiki.trenz-electronic.de/display/PD/Project+Delivery

On the above linked page it states: "Important Note: QSPI Programming need special FSBL on 2017.4 for all Zynq/ZynqMP. Special programming FSBL will be provided on 2017.4 reference designs"

Can someone please explain what changed in 2017.4 that a special FSBL is now required?

And also, what exactly is changed in the FSBL and what is that change trying to fix/workaround?

What exactly are these changes and what are they doing?

JH

Hi,
Xilinx has changes programming steps, since 2017.3 you must add FSBL on Vivado GUI/SDK to program QSPI Flash:
If QSPI is empty and you did not change boot mode to JTAG, you can't get access to QSPI. On older Vivado version this restriction was not needed.

So we add special CPLD to get programming working again on QSPI Boot Mode

Changes see:
Template and prebuilt is also included into the reference design:
See description and download:br
John

PS:

jwdonal

This was helpful thank you. The AR was also useful.

One more question...

In the zynq_fsbl_flash modifications, why is the DDR initialization commented out (disabled) in main.c? I have attached a screenshot.

I uncomment the DDR initialization (i.e. re-enabled it) and the QSPI programming still works fine in 2017.4. It seems that the only modification that is actually required is just adding "BootModeRegister = JTAG_MODE;".

So what is the reason for disabling the DDR initialization?

JH

https://www.xilinx.com/support/answers/70148.html

Quote
If this FSBL is initializing DDR, then DDR needs to be functioning even if the QSPI flash programming does not really use it.

DDR is not needed for Xilinx micro Uboot, which is used to get access to QSPI. So it's faster. You can remove normally much more.

br
John

meisterlampe

Special FSBL for TE0782?

Since the TE0782 only has a reference design for 2017.1:
If i merge the changes within the fsbl of TE0715 (v2017.4) with the fsbl of TE0782 (v2017.1),
will I be able to program the QSPI flash on TE0782 with Vivado 2017.4???

kind regards

JH

Hi,

we are working on 2017.4 updates for all design, but it need a little bit.

To program QSPI Flash with 2017.3 or 2017.4, create a second FSBL (only for the GUI setting on SDK or Vivado), with following changes on main.c (line390):


/*
* Read bootmode register
*/
BootModeRegister = Xil_In32(BOOT_MODE_REG);
BootModeRegister &= BOOT_MODES_MASK;
 
  /* TE Mod : */
BootModeRegister = JTAG_MODE;
  /* TE Mod : finished*/



So FSBL run in JTAG_MODE and starts Xilinx micro Uboot.

Optional you can also disable DDR init, to speed up a little bit.

br
John

meisterlampe

Many Thanks John!

choosing the default fsbl for the boot image and the one modified as you suggested, for the program_flash command, worked right away!
(Additional Info: I had to remove the system variable propopsed by Xilinx AR70148)

Microsoft and Xilinx,
they both keep breaking things that already worked fine in the past! ;)

JH

Hi,
fine that it works.

Quote
Microsoft and Xilinx,
they both keep breaking things that already worked fine in the past! ;)

But is also the same if you use other OS like some of the one million linux distributions or other FPGA manufacturer like Intel(Altera).  Systems will be more complex, but time for development will be shorter and shorter...

I case you would check what Xilinx mini uboot does, add: XIL_CSE_ZYNQ_DISPLAY_UBOOT_MESSAGES=1

br
John