Hi!
Thanks! It's really a sad story..
What do you think about DDR2 ? Looks like its good alternative to LPDDR2 ?
It's available up to 256MB, 0.8 pitch case, termination is optional if 1 chip is used and chips are placed close together. It's also supported by 7series (MIG ans PS).
By the way could you please explain some details about LPDDR2 routing in REV1 ? As I can see both data byte lanes are routed on different layers (top/bot) and lenght match does not exist (~4-5mm difference). Do you perform any kind of simulation for routing verification ? Does any performance problem exist ? Because I see also that in REV2 these things were changed and leght match is exist.
Could you share layout in pdf format and net lenght as separate file, if it's impossible to share entire AD REV2/3 project as opensource ?
Thanks again!