Author Topic: TE0720 JTAG AP timeout over a custom carrier board  (Read 5331 times)

PeVa

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TE0720 JTAG AP timeout over a custom carrier board
« on: March 08, 2018, 08:37:36 PM »
Hello,

I am using Vivado 2016.2 with the Trenz TE0720 in my development system. When the Trenz TE0720 FPGA is installed on the Trenz TE0701 carrier board, I can easily upload the bitstream/elf files/flash memory over the USB interface (FTDI chip/Digilent driver).

When I move the TE0720 board over to my custom carrier board and use the Xilinx JTAG programmer (Platform Cable USB II) I see the following behavior:
1. I can upload a bitstream no problem.
2. If a bitstream has already been flashed, I can upload an elf file in the system debugger.
3. If I try to upload both the bitstream and elf file in the SDK, the bitstream will load, but the elf file will hang with an AP transaction timeout. See attached image.

On my custom carrier board, the JTAG programmer is connected directly to TE0720 pins: JM2-91 (VREF), -93 (TMS), -95 (TDO), -99 (TCK).
CPLD pins: NOSEQ connected to 3.3V (I'm using a single 3.3V supply).
RESIN, MODE, EN1 and PGOOD are not connected to anything.

Since the bitstream is able to load correctly, I don't think there is any issue with the JTAG connection. I noticed the CPLD on the TE0701 interfaces directly to the CPLD on the TE0720. Is there some other signals coming from the TE0701's CPLD that I am not implementing that may be required?

Thanks,
Peter
« Last Edit: March 08, 2018, 09:17:42 PM by PeVa »

PeVa

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Re: TE0720 JTAG AP timeout over a custom carrier board
« Reply #1 on: March 08, 2018, 10:25:01 PM »
I think my main questions are:

1. Do I neet to connect the HALT/PGND pins on the Xilinx Platform CABLE USB II?
2. Does RESIN need to be connected? Should I switch to the TE0790?
3. I noticed the CPLD on the TE0701 interfaces directly to the CPLD on the TE0720. Is there some other signals coming from the TE0701's CPLD that I am not implementing that may be required?

JH

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Re: TE0720 JTAG AP timeout over a custom carrier board
« Reply #2 on: March 09, 2018, 09:10:04 AM »
Hi,

VREF and GND are important. Not PGND, see xilinx Platform cable user guide

Control signals: https://wiki.trenz-electronic.de/display/PD/TE0720+TRM#TE0720TRM-SystemControllerCPLDI/OPins
JTAG_EN must be to set to GND (DIP, pulldown or directly), this is use to get access to CPLD for firmware update. GND means JTAG is routed through CPLD to FPGA (CPLD is like a buffer).
MODE pin is to select QSPI or SD boot, if you not set this only QSPI is selected
Pullup for RESIN, EN1 and PGOOD is recommended, but CPLD as also a weak internal pullup.

Is something on QSPI Flash? Design with linux for example? Something like Linux can prevent access to PS.
So check at first what if something boots.
You can also trx to reduce JTAG speed, maybe it will be better. Or us other USB Port or shorter cable. Xilinx platform cable should also work.

Some Note (not relevant for your problem): If you start app with debugger, PS will be initialised with init scripts. without PS initialisation no PS PL CLK is available. If you create boot.bin fsbl does it (bootrom load FSBL, FSBL init PS, load BItlfile and load App).

br
John


cbr2018

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Re: TE0720 JTAG AP timeout over a custom carrier board
« Reply #3 on: October 01, 2018, 11:39:09 PM »
On my custom carrier board, the JTAG programmer is connected directly to TE0720 pins: JM2-91 (VREF), -93 (TMS), -95 (TDO), -99 (TCK).
CPLD pins: NOSEQ connected to 3.3V (I'm using a single 3.3V supply).
RESIN, MODE, EN1 and PGOOD are not connected to anything.

Isn't that the wrong pin for TDO? On the TE0720 schematic I have, it is on pin 97, not 95. Pin 95 is TDI.

JH

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Re: TE0720 JTAG AP timeout over a custom carrier board
« Reply #4 on: October 02, 2018, 01:58:59 PM »
Hi,
from Module view:
  • JM2-91: output : JTAG_REF(reference voltage)
  • JM2-93: in       : TMS
  • JM2-95: in       : TDI
  • JM2-97: out     : TDO
  • JM2-99: in       : TCK
from carrier view:
  • JB2-92  : in     : JTAG_REF(reference voltage)
  • JB2-94  : out   : TMS
  • JB2-96  : out   : TDI
  • JB2-98  : in    : TDO
  • JB2-100: out  : TCK
see general pinout pictures of:So it depends on the point of view and TDI and TDO swapped can happen quickly.
br
John