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TE0715 2017.4 Board File Bug

Started by jwdonal, March 27, 2018, 02:25:09 AM

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jwdonal

The board files for the TE0715 for Vivado 2017.4 have a minor bug in them. The preset.xml file is missing some necessary lines for properly enabling UART1 peripheral which is causing some strange graphical/customization behavior in the Zynq block design/configurator. If you compare the preset.xml in 2016.2 board files to those in 2017.4 you can see what the missing lines are. I have attached a screenshot for you. I added the missing lines and it's working properly now in 2017.4.

JH

Hi,

i've removed UART1 on 2017.4 board part files. UART1 goes to EMIO, so it's user configuration.  On one of the older Vivado versions, it was needed, because of a bug in petalinux default device tree. But on 2017.4 I did not find any reason to leave them enabled as default, if not used.

br
John

jwdonal

Well then you still have a bug, but it's just the opposite issue. Basically, in the board preset.xml file the UART1 peripheral is half disabled and half enabled which is causing strange vivado behavior in the block design tool.  So in the vivado block design if I use the current board files the UART1 peripheral is half enabled and half disabled.  I have attached a screenshot that shows that the UART1 EMIO port is still being shown on the Zynq PS block even though you think you have disabled it. However, in the configurator it is shown as disabled. Do you see the problem?

So you still have a bug that you need to fix. If you want to completely disable the UART1 peripheral then you need to remove the lines that I have highlighted in my second screenshot.

Your welcome.

JH

Hi,

it's fixed now. New Files should be available in appr. 1 hour. (te0715-test_board-vivado_2017.4-build_07_20180327223552.zip)
It was not visible on the Reference Design BD Files, so i didn't detect this issue.

Thank you very much to pointing that out.


br
John