[TE0950] QSFP help

[hw-lab]

Good evening all!

Recently at my office we bought two TE0950 dev boards.
At the moment we have successfully built the reference design with Petelinux and Vivado 2024.2.
Now, starting from the ref. des.,  we want to explore the QSFP interface by using the Ethernet Subsystem IP configured at 10 Gbps and use it by means of Petalinux. The idea is to start with the reference design of the Eth Subsystem and integrate it with the TE0950 reference design by means of an AXI Smart Connect.
Is there some advice that we have to follow in terms of clock configuration and/or the Artix FPGA design?
Thanks in advance,
Antonio