Author Topic: SD Ram Controller for MAX100  (Read 13637 times)

steveg

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SD Ram Controller for MAX100
« on: December 20, 2017, 09:24:47 AM »
Hello - how do I create a controller for the 8MB SDRAM on the MAX1000 using Quartus?
Thank you
Steve

jefflieu

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Re: SD Ram Controller for MAX100
« Reply #1 on: December 26, 2017, 03:26:52 AM »
Hello,
Have you tried creating a system in Qsys? Then read/write your SDRAM controller via Avalon interface. I think you can then export the Avalon port out of Qsys.

steveg

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Re: SD Ram Controller for MAX100
« Reply #2 on: December 26, 2017, 07:12:43 AM »
Hi - I have not yet purchased a MAX1000 but I would like to purchase many. But for my application  - a camera - I will need the SDRAM. I think it can be difficult to get all the timings right so i was hoping a SD Ram controller had already been developed!
Thanks!

jefflieu

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Re: SD Ram Controller for MAX100
« Reply #3 on: December 27, 2017, 02:52:34 AM »
You can configure the SDRAM controller timing parameter in the Qsys (see attachment)
I was thinking of creating an example that includes SDRAM with MAX1000 board but not had time to do it yet.
If you'd need something to start with, follow the link in my other post.


patk

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Re: SD Ram Controller for MAX100
« Reply #4 on: December 04, 2018, 02:03:50 AM »
How did you setup the SDRAM clock to the W9864G6 chip on the max1000? I added another clock output from the MAX10 PLL to the external pin shown on the user guide, but it doesn't seem to be working.

patk

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Re: SD Ram Controller for MAX100
« Reply #5 on: December 05, 2018, 05:39:19 PM »
Looking at the startup initialization requirements for the W9864 SDRAM and the standard Intel SDRAM controller core operation there looks to be an incompatibility. Was this the FPGA core used to test the interface?

jefflieu

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Re: SD Ram Controller for MAX100
« Reply #6 on: December 29, 2018, 01:59:27 PM »
Have you got it working?
I think I've got it working here.
https://github.com/jefflieu/recon/tree/recon_2/dev/hw
The IO of the MAX10 device can't run beyond 50MHz in single ended mode.

philippe69

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Re: SD Ram Controller for MAX100
« Reply #7 on: November 12, 2022, 10:02:03 AM »
Hello everybody,
Is someone found or wrote a sdram controller ?
I use Quartus Lite edition and the altera_avalon_new_sdram_controller was exclude from this distribution from since the quartus 17 version.
Thank's a lot
Philippe

Thomas D

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Re: SD Ram Controller for MAX100
« Reply #8 on: November 16, 2022, 07:58:49 AM »
Hi,
are you sure that the altera_avalon_new_sdram_controller was excluded from Quartus Lite 17? I have never worked with Quartus Lite 17, but with Quartus Lite since version 18.1 and in every version until 20.1.1 the altera_avalon_new_sdram_controller was included. Each time with the message "SDRAM Controller will only be supported in Quartus Prime Standard Edition in the future release."  Since 21.1 Intel has removed this IP Core from the lite and standard versions.
If you want to use this IP Core in the newer versions, you can just copy the source code of the altera_avalon_new_sdram_controller from an older version into your project (path to source code: <quartus installation path>\intelFPGA_lite\<quartus version>\ip\altera\sopc_builder_ip\altera_avalon_new_sdram_controller). The sdram controller should then be available in the platform desginer. This is how I did it in the reference design with Quartus Lite 21.1:

br
Thomas
« Last Edit: November 16, 2022, 08:04:36 AM by Thomas D »