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SD Ram Controller for MAX100

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patk:
Looking at the startup initialization requirements for the W9864 SDRAM and the standard Intel SDRAM controller core operation there looks to be an incompatibility. Was this the FPGA core used to test the interface?

jefflieu:
Have you got it working?
I think I've got it working here.
https://github.com/jefflieu/recon/tree/recon_2/dev/hw
The IO of the MAX10 device can't run beyond 50MHz in single ended mode.

philippe69:
Hello everybody,
Is someone found or wrote a sdram controller ?
I use Quartus Lite edition and the altera_avalon_new_sdram_controller was exclude from this distribution from since the quartus 17 version.
Thank's a lot
Philippe

Thomas D:
Hi,
are you sure that the altera_avalon_new_sdram_controller was excluded from Quartus Lite 17? I have never worked with Quartus Lite 17, but with Quartus Lite since version 18.1 and in every version until 20.1.1 the altera_avalon_new_sdram_controller was included. Each time with the message "SDRAM Controller will only be supported in Quartus Prime Standard Edition in the future release."  Since 21.1 Intel has removed this IP Core from the lite and standard versions.
If you want to use this IP Core in the newer versions, you can just copy the source code of the altera_avalon_new_sdram_controller from an older version into your project (path to source code: <quartus installation path>\intelFPGA_lite\<quartus version>\ip\altera\sopc_builder_ip\altera_avalon_new_sdram_controller). The sdram controller should then be available in the platform desginer. This is how I did it in the reference design with Quartus Lite 21.1:

* https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/2.5x6.15/TEI0001/Reference_Design/21.1/test_board
br
Thomas

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