SD Ram Controller for MAX100

[steveg]

Hello - how do I create a controller for the 8MB SDRAM on the MAX1000 using Quartus?
Thank you
Steve

[jefflieu]

Hello,
Have you tried creating a system in Qsys? Then read/write your SDRAM controller via Avalon interface. I think you can then export the Avalon port out of Qsys.

[steveg]

Hi - I have not yet purchased a MAX1000 but I would like to purchase many. But for my application  - a camera - I will need the SDRAM. I think it can be difficult to get all the timings right so i was hoping a SD Ram controller had already been developed!
Thanks!

[jefflieu]

You can configure the SDRAM controller timing parameter in the Qsys (see attachment)
I was thinking of creating an example that includes SDRAM with MAX1000 board but not had time to do it yet.
If you'd need something to start with, follow the link in my other post.

[patk]

How did you setup the SDRAM clock to the W9864G6 chip on the max1000? I added another clock output from the MAX10 PLL to the external pin shown on the user guide, but it doesn't seem to be working.

[patk]

Looking at the startup initialization requirements for the W9864 SDRAM and the standard Intel SDRAM controller core operation there looks to be an incompatibility. Was this the FPGA core used to test the interface?

[jefflieu]

Have you got it working?
I think I've got it working here.
https://github.com/jefflieu/recon/tree/recon_2/dev/hw
The IO of the MAX10 device can't run beyond 50MHz in single ended mode.

[philippe69]

Hello everybody,
Is someone found or wrote a sdram controller ?
I use Quartus Lite edition and the altera_avalon_new_sdram_controller was exclude from this distribution from since the quartus 17 version.
Thank's a lot
Philippe

[Thomas D]

Hi,
are you sure that the altera_avalon_new_sdram_controller was excluded from Quartus Lite 17? I have never worked with Quartus Lite 17, but with Quartus Lite since version 18.1 and in every version until 20.1.1 the altera_avalon_new_sdram_controller was included. Each time with the message "SDRAM Controller will only be supported in Quartus Prime Standard Edition in the future release."  Since 21.1 Intel has removed this IP Core from the lite and standard versions.
If you want to use this IP Core in the newer versions, you can just copy the source code of the altera_avalon_new_sdram_controller from an older version into your project (path to source code: <quartus installation path>\intelFPGA_lite\<quartus version>\ip\altera\sopc_builder_ip\altera_avalon_new_sdram_controller). The sdram controller should then be available in the platform desginer. This is how I did it in the reference design with Quartus Lite 21.1:

• https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/2.5x6.15/TEI0001/Reference_Design/21.1/test_board

br
Thomas

[Antti Lukats]

are you sure it is also removed from STANDARD version?

[Thomas D]

It is not listed in platform designer (e.g. 21.1 standard version). See also the attached screenshot (20.1.1 Standard <-> 21.1.1 Standard)

[philippe69]

Hello Everybody,
I asked to Winbond to obtain their SDRAM driver. Find it enclosed.
But, with my level, I couldn't get it to work.

maybe Trenz could help us by providing us with a driver and a design using it ;-))

[dicas3d]

Anyone get the SDRAM controller working on quartus prime lite 22.1.1.

Hi,
are you sure that the altera_avalon_new_sdram_controller was excluded from Quartus Lite 17? I have never worked with Quartus Lite 17, but with Quartus Lite since version 18.1 and in every version until 20.1.1 the altera_avalon_new_sdram_controller was included. Each time with the message "SDRAM Controller will only be supported in Quartus Prime Standard Edition in the future release."  Since 21.1 Intel has removed this IP Core from the lite and standard versions.
If you want to use this IP Core in the newer versions, you can just copy the source code of the altera_avalon_new_sdram_controller from an older version into your project (path to source code: <quartus installation path>\intelFPGA_lite\<quartus version>\ip\altera\sopc_builder_ip\altera_avalon_new_sdram_controller). The sdram controller should then be available in the platform desginer. This is how I did it in the reference design with Quartus Lite 21.1:

• https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/2.5x6.15/TEI0001/Reference_Design/21.1/test_board

br
Thomas

As provided in this post?

[Thomas D]

Hi
@philippe69
we can't help you with these files from winbond, sorry. You should ask winbond for help.

@dicas3d
I have already used the sdram controller in Quartus Lite 22.1.1 as described in my older post and it works the same as in 21.1.

br
Thomas

[philippe69]

I found a solution.
1/ Install the altera_avalon_new_sdram_controller from the 20.1 Quartus
Copy the sdram controller in the quartus folder :
C:\intelFPGA_lite\22.1\ip\altera\sopc_builder_ip\altera_avalon_new_sdram_controller

In bonus, you can get the altera_avalon_new_sdram_controller from the 17.0 Quartus to obtain the sdram list used in the max1000.
Copy TEI0001_sdram_controller.qprs memory in the altera_avalon_new_sdram_controller.qprs file

In the file C:\intelFPGA_lite\22.1\ip\altera_components.ipx add the altera_avalon_new_sdram_controller
<component
   name="altera_avalon_new_sdram_controller"
   file="sopc_builder_ip/altera_avalon_new_sdram_controller/altera_avalon_new_sdram_controller_hw.tcl"
   displayName="SDRAM Controller"
   version="20.1"
   ...

After these operation you will see the SDRAM ip in the QSYS Memory and interface IP Catalog.

2/ Create your design in QSYS
The important thing to know is in the altpll use for the sdram clock MUST have -5000ps of clock phase shift (see the screen capture)
I saw that in the test_board design provides by Trenz :
https://shop.trenz-electronic.de/trenzdownloads/Trenz_Electronic/Modules_and_Module_Carriers/2.5x6.15/TEI0001/Reference_Design/20.1/test_board/TEI0001-test_board-quartus_20.1.1-20210709113644.zip

3/ Find enclose my simple design that is using :
- A Nios programe to light the 4 first leds. It uses user button
- a sdram use
- a verilog program to light the 4 last led

Philippe69