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Author Topic: GTx Transceivers in .xdc - TE0820  (Read 7768 times)

ignacio.moreno

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GTx Transceivers in .xdc - TE0820
« on: December 04, 2017, 09:15:03 AM »
Hi everyone,

when generating the .xdc file with the pinout excel sheet (TE_MASTER_PINOUT.xlsm) for the module TE0820 without base board, also the GT tranceivers are present:

Code: [Select]
set_property PACKAGE_PIN B23 [get_ports B505_TX3_P]
set_property PACKAGE_PIN B24 [get_ports B505_TX3_N]
set_property PACKAGE_PIN C25 [get_ports B505_TX2_P]
set_property PACKAGE_PIN C26 [get_ports B505_TX2_N]
set_property PACKAGE_PIN D23 [get_ports B505_TX1_P]
set_property PACKAGE_PIN D24 [get_ports B505_TX1_N]
set_property PACKAGE_PIN E25 [get_ports B505_TX0_P]
set_property PACKAGE_PIN E26 [get_ports B505_TX0_N]
set_property PACKAGE_PIN A25 [get_ports B505_RX3_P]
set_property PACKAGE_PIN A26 [get_ports B505_RX3_N]
set_property PACKAGE_PIN B27 [get_ports B505_RX2_P]
set_property PACKAGE_PIN B28 [get_ports B505_RX2_N]
set_property PACKAGE_PIN D27 [get_ports B505_RX1_P]
set_property PACKAGE_PIN D28 [get_ports B505_RX1_N]
set_property PACKAGE_PIN F27 [get_ports B505_RX0_P]
set_property PACKAGE_PIN F28 [get_ports B505_RX0_N]

But it is not necessary to add them to the xdc in Vivado, right?

I just ask because I have a problem with USB3 and just want to be sure that that's not the reason. (The USB problem is posted on the Xilinx Forums, just in case someone has interest: https://forums.xilinx.com/t5/Embedded-Linux/USB3-ZynqMP-Linux-Problems/m-p/811147)

Thanks in advance!
I. Moreno
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JH

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Re: GTx Transceivers in .xdc - TE0820
« Reply #1 on: December 04, 2017, 09:46:33 AM »
Hi,

yes PS MIOs and PL GTPs are not necessary on XDC. The data generation of the excel sheet is a semi-automatic process. At the moment we must filter all MIOs manually and i didn't do this for TE0820.

Your USB 3 Problem: Which carrier did you use with TE0820? Our 4x5 Carrier did not support USB3.0. We only activate 3.0 to get 2.0 running on linux (it's only a workaround, if we find out why linux deactivate USB, if USB3.0 is not enabled (I think this has something todo with PMU or device tree)).

A dedicated carrier for TE0820 is in planning, but i can't tell you any timeline at the moment.

br
John
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ignacio.moreno

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Re: GTx Transceivers in .xdc - TE0820
« Reply #2 on: December 04, 2017, 10:12:19 AM »
Hi John,

thanks for your answer!

We are using Trenz's module with a carrier designed by the HW team of my company. The USB 3 signals are connected to GT1 (Rx and Tx) and the reference clock being used is the Ref Clk 3, as in the reference design. There must be some kind of problem with the USB3 signals... The kernel configuration seems to be OK, but when we connect a USB3 device, its absolutely not working.

Regards,
Ignacio
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JH

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Re: GTx Transceivers in .xdc - TE0820
« Reply #3 on: December 04, 2017, 10:46:37 AM »
Hi,
did you use our board part files and our modified FSBL?
GTP reference clks are sourced by SI5338. We have a 2017.2 example design only (default with our FSBL 100MHz on REFCLK3):
We have a other Module Series TE0803, with working USB3.0. And TEBF0808 as carrier. You can check this schematics with your schematics/pcb design:br
John
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ignacio.moreno

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Re: GTx Transceivers in .xdc - TE0820
« Reply #4 on: December 04, 2017, 10:58:47 AM »
Hi John,

yes, I took your board files from the reference design you indicated and also the modification of the FSBL. Actually, I am using REFCLK3 because is the one programmed with your modified FSBL. The clock doesn't seem to be the problem since the kernel indicates that the PLL is being locked. Also all USB drivers get initialized properly.

Device tree:

Code: [Select]
usb0 {
#address-cells = <0x2>;
#size-cells = <0x2>;
status = "okay";
compatible = "xlnx,zynqmp-dwc3";
reg = <0x0 0xff9d0000 0x0 0x100>;
clock-names = "bus_clk", "ref_clk";
#stream-id-cells = <0x1>;
iommus = <0x7 0x860>;
power-domains = <0x24>;
ranges;
nvmem-cells = <0x17>;
nvmem-cell-names = "soc_revision";
clocks = <0x3 0x20 0x3 0x22>;

dwc3@fe200000 {
compatible = "snps,dwc3";
status = "okay";
reg = <0x0 0xfe200000 0x0 0x40000>;
interrupt-parent = <0x4>;
interrupts = <0x0 0x41 0x4 0x0 0x45 0x4>;
snps,quirk-frame-length-adjustment = <0x20>;
snps,refclk_fladj;
dr_mode = "host";
snps,usb3_lpm_capable;
phy-names = "usb3-phy";
phys = <&lane1 0x4 0x0 0x2 0x5f5e100>;
};
};]
Code: [Select]
[    3.098390] xilinx-psgtr fd400000.zynqmp_phy: Lane:1 type:0 protocol:3 pll_locked:yes
I configured this way a ZCU102 from Xilinx and a custom board with ZynqUltrascale+ and they both worked properly with USB3, so I discarded that this is a problem related to the configuration of the embedded Linux.

Thanks a lot for the hint! I will keep you updated if we find out what the problem is.

Regards
Ignacio
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JH

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Re: GTx Transceivers in .xdc - TE0820
« Reply #5 on: December 04, 2017, 11:08:45 AM »
Hi,

so CLK is ok.

On TE0803  there was no additional device tree entry necessary for USB3.0 with petalinux 17.1 (But this can change form one petalinux version to the next). Maybe you can try one time without your entry.
But you should also check your schematics with our TEBF0808 schematics.
PS: You can also reconfigure CLKs, like you need it. Short description is on the wiki link.

br
John
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ignacio.moreno

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Re: GTx Transceivers in .xdc - TE0820
« Reply #6 on: December 04, 2017, 11:40:13 AM »
Hi John,

what you mention about device tree is really interesting. I am also using Petalinux 2017.1 to get a template of the device tree. Then, I modify this template according to my project (for example, to add "spidev" devices or to set parameters of different Linux drivers).

If I don't modify the device tree for USB with the TE0820 + our carrier, USB is working perfectly, but as an USB2 device. USB3 peripherals also work, but as USB2 peripherals (in compatibility mode). So, I modify the device tree to tell the Linux driver that my USB is 3.0 . The modifications are:

On the node dwc3@fe200000 (USB Phy), which is inside the node usb0, I include these lines:

snps,usb3_lpm_capable; #to indicate that USB3 is compatible with link power management
phy-names = "usb3-phy"; #to indicate that there is a USB3 Phy (in this case the zynq)
phys = <&lane1 0x4 0x0 0x2 0x5f5e100>; #phy configuration

It would be really helpful for me if you could confirm that in your case USB is working as USB3 host. Could I have a look at the device tree (.dts or .dtc)?

Thanks in advance,
Ignacio



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JH

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Re: GTx Transceivers in .xdc - TE0820
« Reply #7 on: December 04, 2017, 01:43:47 PM »
Hi,

With USB3 memory stick, he detect Super Speed USB. With USB2 memory stick, he detect high-speed USB.
We use USB3.0 HUB on TEBF0808:br
John
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ignacio.moreno

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Re: GTx Transceivers in .xdc - TE0820
« Reply #8 on: December 04, 2017, 05:33:07 PM »
Hi John,

I extracted the device the "image.ub" of your the petalinux project you referenced. I am surprised that usb3 works without reference to the GT transceivers on the device tree, but unfortunately I cannot investigate why because I don't have that module... I posted on Xilinx forums with my doubts about usb 3 device tree: https://forums.xilinx.com/t5/Embedded-Linux/USB3-ZynqMP-Linux-Problems/m-p/811147

I will also check the schematics with my HW colleagues.

Thanks a lot for your interest. I will keep you updated!

Regards
Ignacio
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