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TE0712 SI5338 Programming

Started by goli12, November 30, 2017, 02:12:29 AM

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goli12

Hi there

I am a bit confused with programming the SI5338 through i2c.
From the procedure on the SI5338 data sheet, page 23, it says that OEB_ALL needs to be set to disable all outputs.
Upon writing to that register, my module hangs and I have to power cycle before reprogramming.

Probing the chip with an oscilloscope in this state did not show any of the clocks being generated, which I suspect
is the cause of the hang.

I am using a TE0712 4x5 module with the reference design. The C code is shown below:

#include "xparameters.h"
#include "xiic_l.h"
#include "xiic.h"
#include "xintc.h"
#include "xil_exception.h"
#include "xil_printf.h"

#define IIC_BASE_ADDRESS XPAR_IIC_0_BASEADDR
#define IIC_DEVICE_ID    XPAR_IIC_0_DEVICE_ID
#define SI5338_ADDRESS  0x70

/************************** Function Prototypes ******************************/

int IicSetup(u16 DeviceId);
/************************** Variable Definitions *****************************/

XIic Iic;

int main(void){

int value;
int i = 0;
int status;
u8 tx_data[2];
u8 reg_value;
u8 rx_data;
//int* reg_value_pointer;
//int* test;

xil_printf("/***** Si5338 write test ******/\n\r");

/* IIC setup */
status = IicSetup(IIC_DEVICE_ID);
if(status == XST_FAILURE){
xil_printf("setup failure \n\r");
xil_printf("/***** done ******/\n\r");
return XST_FAILURE;
} else{
xil_printf("setup passed \n\r");
}


tx_data[0] = 230;
reg_value = 0b10000;
tx_data[1] = reg_value;

xil_printf("writing to 0x%x\n\r",tx_data[0]);
XIic_DynSend(IIC_BASE_ADDRESS, (u16)SI5338_ADDRESS, &tx_data,(u8)2,XIIC_STOP);


xil_printf("calling DynSend\n\r");
XIic_DynSend(IIC_BASE_ADDRESS, (u16)SI5338_ADDRESS, &tx_data,(u8)1,XIIC_STOP);

xil_printf("calling DynRecv\n\r");
xil_printf("bytes received: %d\n\r",XIic_DynRecv(IIC_BASE_ADDRESS, (u16)SI5338_ADDRESS, &rx_data, (u8)1));

xil_printf("rx_data: 0x%x\n\r",rx_data);


xil_printf("/***** done ******/\n\r");

return 0;
}

int IicSetup(u16 DeviceId){

int Status;
XIic_Config *ConfigPtr; /* Pointer to configuration data */

/*
* Initialize the IIC driver so that it is ready to use.
*/
ConfigPtr = XIic_LookupConfig(DeviceId);
if (ConfigPtr == NULL) {
return XST_FAILURE;
}


Status = XIic_CfgInitialize(&Iic, ConfigPtr, ConfigPtr->BaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}

return Status;

}


As shown, I am interfacing the SI5338 through Xilinx's IIC.
I am also able to read and write to some of the registers as well.
I appreciate any feedback and suggestions.

Regards
Andrew


JH

Hi,
which CLK did you need for your microblaze? SysCLK from Reference Design is also from SI5338. So if you reset SI5338 any CLK is missing.
Must try to change only the other outputs settings which has no affect of Microblaze Reference CLK.  Or you must add a small Microblaze/MCS  with internal programming CLK (available over startup primitive), connect to I2C and program with this.
I will prepare a example (but need a little bit time there are to much other tasks at the moment)
br
John

goli12

Hi John

At the moment, I am using the reference design which uses CLK3A and CLK3B from Si5338 to the MIGs.
The microblaze in the reference design uses ui_clk from MIGs.

The problem with using other clock capable pins on the TE0712 is that for the MIGs block, it requires a clock that is in the same column as the memory interface as per AR# 40603 from Xilinx. Hence the only clock pins I can use is on H4 and G4. K4 and J4 can also be used as well which is connected to CLK0A and CLK0B. However the default configuration on the Si5338 does not generate any clock and since it cannot be programmed at the mean time, it also cannot be used.

I hope this helps, and I am looking forward to your response.

Regards
Andrew

JH

Hi,
default SI generate CLKs:
You can use our 2017.2 Reference Design (with prebuilt files):You can't use any CLK of SI5338 for you Microblaze Design, if you reset SI5338. So add for example MCS and use startup primitive (get access to configuration clk over internal FPGA Primitive, no IO). Or you must change only some register for outputs(not this clk for MIG) without reset PLL
br
John

goli12

#4
Hi John

I am currently using TE0712 2017.2 reference project. My intention is to change the input clock of the SI5338 from the onboard 25 MHz oscillator on IN3 of the Si5338 to a differential clock routed JM3-32 and JM3-34 which connects to IN1 and IN2 of the Si5338. I would like to leave the outputs as default. However, doing so will require the Si5338 outputs to be disabled as shown in figure 9, page 23 in the Si5338 datasheet.

Re-writing the registers with the values to change the input from IN3 to IN1 and IN2 without following the procedure on the datasheet did not reprogram the Si5338.

How would I go about changing the Si5338 input clock from IN3 to IN1 and IN2 with a startup primitive if I will be disabling all output clocks during the reprogramming procedure?

Regards
Andrew


goli12

Hi John,

Please disregard the previous comment.
I understand the new procedure, and I will come back if I have anymore questions.

Regards
Andrew

JH

Hi,

i've update test board design with SI5338 programming and eth. Download should be available in appr. 1 hour.
br
John

goli12

Cheers John, I appreciate the effort for getting the example design out.

Regards
Andrew

goli12

Hi John

I made a new C code header file from SI clockbuilder tool, which configures the Si5338 to use IN1/2 instead of the on-board oscillator. Following my previous replies, I want this to occur on FPGA startup. From the procedure outlined in https://wiki.trenz-electronic.de/display/PD/TE0712+Test+Board#TE0712TestBoard-Content, the last step says "Replace Header files from FSBL template with generated file". I was wondering where is this header files so I can replace them with my generated C code header file from the clock builder tool?

Regards
Andrew

JH

Hi,

MCS configures the SI5338 with SCU Firmware. SCU source path is missing in the description, I will add this. Replace test_board\sw_lib\sw_apps\scu\src\register_map.h with your generated register file.
Update your Bitfile with new MCS Firmware or regenerate design, see Step 9 and 11:
br
John