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TE0712 - No devices detected on target - through JTAG

Started by pratik, November 10, 2017, 06:45:29 AM

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pratik

Hi,
     By mistake I have connected JTAG PINS TDO, TDI, TMS ,TCK  to ground pin of xilinx Platform Cable USB II  and powered up the TE0712 board. After that I have connected JTAG Pins correctly but now I am getting error no devices detected on target localhost:3121. So I want to know is there any possibility of damage on CPLD JTAG PIN or FPGA JTAG PIN by connecting JTAG (TDO,TDI,TMS,TCK) Pins to ground pins of xilinx Platform Cable USB II. Please guide me.

JH

Hi,

when you connect it to GND, i think no. If it was VDD or so it can be.
Which carrier did you use?
Did you check direction of TDI and TDO, maybe this is swapped. Did you connect correct reference voltage and the GND Pin?

br
John

pratik

Hi JH,

We had designed our own custom board, with JTAG signals exposed. While connecting JTAG through connector to the Platform Cable, the pins got connected diagonally opposite. ie., Vref from FPGA got connected to PGND of platform cable, and TDI, TDO, TCK and TMS pins got connected to the GND pins of platform cable. We realized this later, and when we tried connecting it back, Vivado labtools complained about getting 0's on device ID. Further we probed the TDI pin, which seems to be stuck at 0. I believe since Vivado is unable to get device ID, it will not be able to proceed further for programming.

We do have TE703 baseboard as well with us. When using the TE712 with this baseboard, we get the same error, that deviceID contains all 0s.
However the FPGA seems to be loading default bit file from QSPI flash and running it well. Is there a way for us to access the QSPI other than from JTAG? This way we could load bitfile to the flash and use the FPGA, since FPGA is able to load bitfile from flash.

Thanks for your quick response.       

JH

Hi,

.
With "VREF from FPGA" did you mean TE0712 Module Pin JM2-91? So you connect 3.3V to PGND of the Platform Cable


For TE0703:
Can you tell me DIP settings?
Note if you have the older Firmware on TE0703, S2-3 is important.
At first we should try to get access to Module with TE0703. If this not work, than your JTAG is damaged or something is with you JTAG Driver or so.

Did JTAG works from TE0712 with TE0703, before you connect JTAG on wrong way?
Which Vivado version do you use? Which OS? Do you use VM or native? Do you have a working setup of TE0703 with TE0712?

br
John

pratik

Hi JH,

I have connected VREF from FPGA(TE0712 Module Pin JM2-91) 3.3V to PGND of the Platform Cable. We tried to get access to Module with TE0703 but no devices detected on target. JTAG was working with our custom base board before I have connected JTAG in wrong way.

Vivado version :2015.4 and 2017.3
OS: Windows 7


JH

Hi,

ok, if it works before you connect JTAG in the wrong way, than it can be damage. GND shouldn't matter. Maybe something else was connected.
Can you measure the 3.3V from module? Is this available and correct?

If JTAG is damaged, you can't get access to Flash with external tools. Access over FPAG Design is possible, but you can't change this, so this is only theoretical option for you.   

br
John

pratik

Hi JH,
            3.3 volt is there on VREF pin from TE0712(JM2-pin 91).

JH

Hi,

last idea, if this not works, JTAG is damage.

Note: On TE0712 JTAG is routed through CPLD, if you have damaged JTAG, than CPLD Pins.

br
John

pratik

Hi John,

Thanks for your prompt reply. I was able to flash new CPLD firmware to TE703. However, after changing S2 dip switch configuration to access module CPLD,  Lattice Diamond programmer throws error. This is the same error (deviceID being 0), which we had seen earlier in the Vivado tools. I suppose the CPLD is damaged. In that case, can we replace CPLD and check if we can access FPGA JTAG?

JH

Hi,

yes, I think this should be work. But I can't promise it.
Replace CPLD and configure with TE0712 CPLD firmware.

br
John

pratik

Hi JH,
          We will try and let you know.

pratik

Hi John,

We have replaced the CPLD and programmed with new CPLD firmware which is posted above. Now we are able to detect the Xilinx FPGA, however we are not able to program it. It gets stuck at 1% programming. Any clue as to what might be the problem?

JH


pratik


JH

Hi,

can you measure basic power? Maybe something is damaged during replacing of CPLD. Can you check CPLD Pins an components around cpld?

br
John

pratik