Author Topic: DEMO MAX1000: Implementation of the soft core "NiosII"  (Read 3772 times)

PowerUser

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DEMO MAX1000: Implementation of the soft core "NiosII"
« on: November 03, 2017, 01:40:05 PM »
MAX1000: Implementation of soft core "NiosII" from Intel FPGA

The guide is the perfect starting point for first time implementing a soft core into an FPGA and program this core with standard ucontroller language C.
It will show you how easy it is to run a soft core in a MAX10 FPGA.

PS: The used USB Blaster programming tool and driver, is licensed by Arrow Electronics and in combination Trenz Electronic products. It is not allowed to use this driver/IP for own products/purposes. Please read the Arrow license agreement carefully.

Please download the project here:
https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/2.5x6.15/TEI0001/Reference_Design
« Last Edit: February 23, 2018, 09:45:21 AM by Thorsten Trenz »

giuliof

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Re: DEMO MAX1000: Implementation of the soft core "NiosII"
« Reply #1 on: May 27, 2018, 05:20:42 PM »
Hi
I'm having some troubles with MAX1000 and NiosII.
I noticed that touching the board or plastic headers shell causes resets both in demo at startup (everytime) and in some of my projects (rarely).

I followed your guide, with the only difference that I added SDRAM support instead of On-Chip RAM because memory was not enough for my pourposes. At first, for some weeks, I had no problems. Now I have the board continuously resetting after loading my code from Eclipse.
I also tried with an external pullup on reset pin or moving the reset on another GPIO. In second case execution time is longer but hangs anyway after a while (5 ~ 6 s).

I can't get any info from the debugger, maybe because I'm looking in the wrong place.

Thank you for any info.
~ giulio

Vlad

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Re: DEMO MAX1000: Implementation of the soft core "NiosII"
« Reply #2 on: October 24, 2020, 09:37:20 AM »
Hi,

Thank you for this guide.

I am trying to reproduce this with my TEI0001 board on Windows 10 Home laptop. I understand there are couple of mistakes, like pll_locked shall be pll_locked_conduit and that the text instructions on how to interconnect IPs in Quartus do not fully correspond with the screenshots. However, I was able to complete Quartus piece of it and upload to the FPGA board.
Then I continued with Eclipse portion of it and failed on the very last step of downloading  the code into the memory of the MAX10.
I tried Quartus 17.0 and 18.1, the same error, tried Arrow USB Programmer 2.3 and 2.4, no luck. Also followed some hints I found on Internet, but it does not work. I do not know what is the cause, if a sort of incompatibility of Arrow USB with Qaurtus/Eclipse or something else, like a wrong IPs interconnect or something.

I do not have any other board I could try with. Also do not have any other programmer, only TEI0001 board.

I am attaching screenshots of Eclipse download error,  screenshots of Target Connection and System ID pull.

Any help is appreciated.
« Last Edit: October 24, 2020, 09:39:12 AM by Vlad »

t.dueck

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Re: DEMO MAX1000: Implementation of the soft core "NiosII"
« Reply #3 on: October 26, 2020, 08:15:18 AM »
Hi,
Thank you for this guide.
Which project/guide are you talking about exactly? I can see several projects in the link mentioned in the first post of PowerUser.

I am attaching screenshots of Eclipse download error,  screenshots of Target Connection and System ID pull.
It seems that the screenshots are missing in your post. I can't see them.

br
Thomas

Vlad

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Re: DEMO MAX1000: Implementation of the soft core "NiosII"
« Reply #4 on: October 26, 2020, 07:41:11 PM »
Hi Thomas,

I am referring to this:
https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/2.5x6.15/TEI0001/Reference_Design/16.1
MAX1000 Nios II Core Lab.zip

I attached screenshots as attachments and they are waiting for an approval from administrator.
I guess a direct insertion of an image is not possible. I am new to this forum, when I click Insert Image button I just get this .


Thx,
Vlad




Vlad

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« Last Edit: October 26, 2020, 07:56:26 PM by Vlad »

t.dueck

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Re: DEMO MAX1000: Implementation of the soft core "NiosII"
« Reply #6 on: October 27, 2020, 08:56:49 AM »
Hi Vlad,
it looks like the clock source is missing or your nios design is hold in reset.
Are your Pin assignments correct? It seems that the part how to set the pin assignments is missing in the 'MAX1000 NIOS User Guide.pdf'.
After running 'Analysis & Synthesis' the used I/O pins should appear in the Pin Planner ("Assignments -> Pin Planner" from quartus top menu). It should look like the attached screenshot.

In the "MAX1000 NiosII Core Lab.zip" file is also a completed design (max1000_nios_lab_completed.7z). You can open the max1000_nios_lab_completed.par file with quartus and program your device with that design. If you don't get download errors in eclipse you can compare your design with the completed design to find the differences.

br
Thomas

Vlad

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Re: DEMO MAX1000: Implementation of the soft core "NiosII"
« Reply #7 on: October 27, 2020, 07:35:19 PM »
Hi Thomas,

You've made me very happy  :D

I felt there were some mistakes in the guide and I could not take it blindly as a step by step guide, but my knowledge is not that high that I would reveal all the mistakes.

I did not realize there was a complete design available in the ZIP file that I could use. Thank you for having it pointed out.
I used it, I restored it in Quartus, programmed FPGA board and uploaded the code for Nios II via Eclipse.
It works.
I am so glad.

Now I need to compare my 'failed' design with the right one to see what was wrong, and play further with Nios II while writing my own code. Lots of fun ahead  ;)

Many thanks, appreciate your time spent on it and also how directly you went to the right point.

Vlad