[TE0726 Zynqberry] ZynqBerry Raspberry PI Camera V2

[cuongtv]

Hi All,

I have ran Design example [ZynqBerry - Demo VIDEO/AUDIO Design with RPI video camera stream to monitor]. It work fine witd RPI V1.3. Let me ask a question:

Can I run this example with  RPI video camera V2 (8M)? if not, how can I fix it?

Thanks so much!

[Oleksandr Kiyenko]

Hi,

last versions for Vivado 2017.1 should work with both camera versions. https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/TE0726/Reference_Design/2017.1


Best regards
Oleksandr Kiyenko

[cuongtv]

Thanks ^^

[orf2hi]

Hi,

After building the reference design for 2017.1 (zynqberrydemo1, https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/TE0726/Reference_Design/2016.2/te0726_m_demo1).
I am able two see the camera frames on my monitor. As mention on this web, almost half of the frames are corrupt (Restrictions (Beta Status):   Camera Rev 2.1: Not complete stable).

Do you have more information about this issue,? some clue about what is causing this problems? planning of next version of a Trenz reference design? have someone else solved the problems-?
Thanks a lot in advance.

[Oleksandr Kiyenko]

Hello,

The reason of this issue is that this core is made mostly based on reverse enginering of CSI interface. With old camera version it's working pretty good, but new camera have much higher interface speed.
The main problem that camera configuration used have high datarate and big pauses between lines and frames. There is two possible ways to solve this issue, first is to modify calibration system for stable work on
higher datarate, second is to rewrite camera configuration to decrease interface datate and reduce pauses.

Best regards
Oleksandr Kiyenko

[gtx]

Hi Oleksandr,
is it possible to use the Xilinx D-PHY-IP since it is for free?

Best regards

[Oleksandr Kiyenko]

Hello,

I try to replace my core by D-PHY from Xilinx, it's not working at first try. Unfortunatelly I have no time now to debug it further.

Best regards
Oleksandr Kiyenko

[gtx]

Hi,
the Xilinx D-PHY IP requires LP-Signals to be connected. As far as I can see there are no LP-Signals on the ZynqBerry at all. How did you solve this issue?

[Oleksandr Kiyenko]

Hello,

Zynqberry have one paar LP signals for D0, D-PHY expect LP for all signals. I connect all LP signals in parallel, but looks like it's not working.

Best regards
Oleksandr Kiyenko

[gtx]

Oh you are right,
but what about the clock lane lp signals? The clock lane is running in burst mode. Is there a setting in the Imager to run the clock in continious mode?