No GTX REFCLK3 on TE041, hardware issue?

[xetnik]

Hi everyone,

I am using the TE0741-160-2CF together with the TEBA0841. I am able to get a signal from the clock sources GTX REFCLK1 and Bank 14 input clock but not GTX REFCLK3 (naming from the TE041 TRM page 9). I have enabled the PLL reference via the CLK_EN Pin C26 on the FPGA.

I measured the clock signals on the U2 Si5338 Chip and also there I only get the clock signals from CLK0A/CLK0B and CLK1A/CLK1B (naming from the Si5338 Datasheet). Is there something I am missing, do I have to activate the MGTCLK3 in a special way or is this a hardware issue?

Also, where do I find the right IOSTANDARD properties for these clock pins (LVDS_25/LVCMOS33)?.

Thank you in advance and best regards,
xetnik

[JH]

Hi,

Si5338 CLK2(for MGTCLK3) is default not configured. See:

• https://wiki.trenz-electronic.de/display/PD/TE0741+TRM#TE0741TRM-ProgrammablePLLClock(Phase-LockedLoop)
• https://wiki.trenz-electronic.de/display/PD/TE0741+TRM#TE0741TRM-Clocking

CLK0 IO Standard LVDS
CLK1 und CLK2 for MGT Ref did not need this property.

PLL can be reconfigured over I2C. At the moment we have no example online. We will add one on the 17.1 reference design (working in process, not available at the moment).
We do the same with TE0841. You can check this example.
Procedure:
1. Add MPU with GPIO to I2C
2. Generate Firmware with I2C configuration (see TE0841)

To get correct register file for SI5338 configuration, use SI5338 ClockBuilder Desktop from Silicon Laboratories.


br
John

[xetnik]

Dear John,

Thanks for your reply, I appreciate your help.

BR