Author Topic: Problems using DSI on Zynqbeery  (Read 1690 times)

SoftwareProjekt

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Problems using DSI on Zynqbeery
« on: August 01, 2017, 11:06:11 AM »
Hi,
is it possible to fully operate a Raspberry Pi DSI display with the zynberry board ?
If so, would it be possible for you to provide a demo design for the application ?
Or could you please provide a DSI IP ?

Greetings
SoftwareProjekt


Oleksandr Kiyenko

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Re: Problems using DSI on Zynqbeery
« Reply #1 on: August 07, 2017, 12:11:42 PM »
Hello,

it's possible, because Zynqberry have proper connector and signal routing. Problem is that DSI specification is not public and we have no access. Also RPI display control is
not well documented. Sorry, but we not provide any project/IP for DCI.

Best regards
Oleksandr Kiyenko

gasfis

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Re: Problems using DSI on Zynqbeery
« Reply #2 on: November 19, 2020, 06:32:13 PM »
Hi,

Tried to do this and did some work and reading before seeing this topic.
Got stuck on creating constraints, will give more details at the end.

Started by trying to use the Xilinx MIPI DSI Transmitter Subsystem IP core that now comes with Vivado for free.
I'm still working with 2019.1 and an evaluation licence.

I took the Trenz demo 1 design and simply added an AXI4 Stream Broadcaster IP before the "video_out" hierarchical block of the demo 1 design.
The view is to share the incoming stream to both the existing "video_out" and a new Xilinx MIPI DSI Tx block.
Added the new Xilinx MIPI DSI Tx block with 2 lanes, the block requires some AXI connections and clocks but I wanted to focus on the external pins.
2 lanes and clock differential are 6 pins, but it there are 2 sets of them, LP and HS.

The z7010 doesn't have a specific DSI PHY and it seems that TE0726-03M PCB has implemented the resistor network suggested in Figure 10 of XAPP894,
This can be seen I think in pages 3,8 and 11 of the schematics pdf and a similar strategy has been used for the CSI-2 camera Rx.
The problem I have is that pins related to the camera Rx are wired on z7010 pins, whereas some of the DSI pins are terminated on the LCMXO2-256HC-4SG32I (page 8 of the schematic).
Following the easy way of separating LP and HS from https://forums.xilinx.com/t5/Video-and-Audio/SP701-MIPI-CSI-and-DSI-on-different-IO-banks/td-p/1162512, it seems that the HS pins are the ones connected to the z7010 and the LP the ones on the LCMXO2.

So the first question is how can I access the LP pins connected to the LCMXO2 or how should my DSI constraint file be?

On the other hand have I misunderstood sth fundamental?
The constraints _i_csi.xdc of the CSI-2 interface in the demo1 example do not contain several of the pins one would expect to see (e.g. the negative of the CSI clock)

Thank you



Oleksandr Kiyenko

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Re: Problems using DSI on Zynqbeery
« Reply #3 on: November 20, 2020, 01:02:25 PM »
Hi, gasfis,

If you want to use signals connected to the LCMXO2 CPLD chip you will need to modify this chip firmware.
It's possible to share the Lattice Diamond project for this chip by request.
If you going to do that, please write a request to support@trenz-electronic.de

Best regards
Oleksandr Kiyenko

gasfis

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Re: Problems using DSI on Zynqbeery
« Reply #4 on: November 22, 2020, 09:50:57 PM »
Hi Oleksandr,

Many thanks for the reply.
I'm using it for learning purposes so won't try to go that deep in changing the Lattice firmware.
Found a DPI screen and will try to use that one.
Think I've found a couple of stray pins there, but will post another topic for it.

Nice work on the HDMI IP cores in the example design by the way.
I really enjoyed following their functionality.

Best regards

Giorgos

Antti Lukats

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Re: Problems using DSI on Zynqbeery
« Reply #5 on: March 16, 2021, 10:53:55 AM »
I think the default CPLD firmware does not support the DSi usage at all, so it needs to be modified first.