TE0720 LED site

[gordon]

I checked the schematic of TE0720 and found that the green ULED is mapped to MPIO7 pin. When I looked up the schematic the pin is connected to P11 and D5 in various banks. I wrote a code in verilog using vivado to blink the LED. But during implementation it gives me that the LOC site is not valid for both D5 and P11. Which pin is actually connected to the FPGA that I can program with?

[JH]

Hi,

TE0702? Did you mean TE0720?

br
John

[gordon]

Sorry, Yeah TE0720

[JH]

Hi,

can you send me the link to the schematic, which you has used?

D2(Green) --> LED1 --> connected to CPLD  Pin  P2
D5(RED) --> LED2--> connected to CPLD  Pin  N3
D4(Green) -> DONE -->  this can online controlled over startup primitive after FPGA configuration, if FPGA is in user mode.

FPGA Pin P11 is VCCAUX

see for example page 6 and 2:
https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/TE0720/REV03/Documents/SCH-TE0720-03-1CF.PDF


LED description: https://wiki.trenz-electronic.de/display/TE0720/On-board+LEDs

LED1 is mapped to MIO7 after power up, you can access via PS-GPIO for example.This is a dedicated PS Pin and need no LOC constrain. Must only enabled on PS GPIO for this Pin and export design to SDK. Use Xilinx examples for access.

br
John