Author Topic: TEBF0808 - 2017.1 Vivado Files not working  (Read 6773 times)

wara154

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TEBF0808 - 2017.1 Vivado Files not working
« on: June 22, 2017, 10:47:30 AM »
Hello,

I have a problem using your recently released 2017.1 Vivado Files (te0808-Carrier_TEBF0808-vivado_2017.1-build_02_20170621131218.zip) after setting up a PetaLinux Project of my own and generating U-Boot/Linux with it the TEBF0808 wouldn't boot.
The next thing I've tried was to use the prebuilt files contained in the .zip file. I copied both the BOOT.bin and image.ub to the SD Card, still without success... I've tried all the prebuilt U-Boot Versions to be sure that I didn't use the wrong one accidentally.

Are the 2017.1 files verified to be working? Am I overlooking something?


Kind Regards
wara154

JH

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Re: TEBF0808 - 2017.1 Vivado Files not working
« Reply #1 on: June 26, 2017, 12:04:49 PM »
Hello,

can you tell me which TE0808 assembly option you has? ES1 or ES2 device? And ES2 with speed grade -2?
Memory options has changed on Vivado again. On older versions of Vivado memory settings work for all assembly versions. So we test only with one (ES2 with speed grade -2) to get the new settings.

br
John   

wara154

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Re: TEBF0808 - 2017.1 Vivado Files not working
« Reply #2 on: June 26, 2017, 02:29:41 PM »
Hey,

we have an ES1 device.

Kind Regards
wara154

JH

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Re: TEBF0808 - 2017.1 Vivado Files not working
« Reply #3 on: June 26, 2017, 04:56:13 PM »
Hi,

memory setting works with ES1 (RAM-Test and hello World via SDK with reduced  PS settings (PS Interfaces with MGTs disabled)). It seems to be the FSBL, at the moment I've problem to start up FSBL via SDK in debug modus. I will inform you, when I find out what's happens exactly.
br
John

JH

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Re: TEBF0808 - 2017.1 Vivado Files not working
« Reply #4 on: July 14, 2017, 03:06:34 PM »
Hi,

you can change the DDR settings, like that one the screenshot at the attachment. Regenerate bitfiles, fsbl and boot.bin with this settings. A other customer has send us this configuration for ES1. DDR will be slower like on older Vivado Designs, but it should work. It seems is something wrong with higher speed, which is not checked by xilinx default ddr test.
 

I will generate new boart part files and update reference design during next week. We found also some new  PS settings on Vivado 2017.1 ZynqMP IP (they wasn't available on 16.4), which are default not correct. So I would recommend to use our new board parts after my update.

br
John