ZynqBerry TE026 Ethernet implementation

[mugurumov]

Hi there,

I want to start tinkering with the Zynqberry board. I have seen that the board uses a USB - Ethernet adapter to make use of the USB and Ethernet.
Now  I would like to implement Gb Ethernet into the board, not using this chip at all, "natively".

As I have seen, there is plenty of pins to use + the PL is not loaded at all. So it might be possible to set 8 GPIO pins, 2x pairs for TX and 2x for RX, to connect an Ethernet wire.
As far as I understand, it would be possible to:

1) Make use of the Zynq Ethernet Controller (called Enet 0 & 1 I think)
2) Implement all at the PL, using some IPs and the AXI inteconnection + DMA.

I have found an example here:
https://www.xilinx.com/support/documentation/application_notes/xapp1082-zynq-eth.pdf

But most of the examples doesn't work under Vivado 2016.2. And I have noticed, that they're using SFP instead of typical RJ45.

One of the problems I'm seeing is that I cannot find any IP dedicated to convert MII interface to RX/TX.

Is it possible to do this? Or there are reasons to not doing so? (Electrical reasons for instance: pin protection, voltage levels, ...)

Thanks in advance

[Oleksandr Kiyenko]

Hello,

You can't directly connect GPIO pins to Ethernet wire.
Only way to do that is to use GPIO pins from FPGA bank 34 connected to some external Gigabit Ethernet PHY chip.
As for Vivado project, there is 2 solutions:
1. Use Zynq PS ethernet controller, it should be configured to EMIO, than in PL part it should be routed (probably using RGMII) to external pins
2. Use AXI 1G/2.5G Ethernet subsystem also conneted to external GPIO pins

Best regards
Oleksandr Kiyenko

[mugurumov]

Hi Olekandr,

Thanks for you reply. That's what I was suspecting. I think I would look for a Gb Ethernet PHY Eval board to attach to GPIOs.

Regards

[mugurumov]

I've started implementing it.

So as you have pointed out, I have been digging a bit into the free pins of the Zynqberry. I understand that the internal traces I have to use are the EMIOs connected to the bank34 you've mentioned (the actual physical pins that makes connection with the GPIO header).

So I have configured out the Zynqberry to have Enet0 into EMIOs. I have also clikced on MDIO an also assigned to EMIO. This way I cant route those pins to the GPIO header pins.

Now I have placed a MII to RGMII IP core and also a SelectIO Wizard to convert MDIO 3x signals I,O & T into a IO MDIO signal. To do so I have followed the next docs:

+ https://www.xilinx.com/support/documentation/ip_documentation/gmii_to_rgmii/v4_0/pg160-gmii-to-rgmii.pdf

-> Specially helpful the picture of page 16, Figure 2-7

+ https://forums.xilinx.com/t5/General-Technical-Discussion/MDIO-connection-between-MAC-and-Internal-PHY-Ethernet-1000base-X/td-p/492758

and here this image:


So I have ended up with this connections at the PL (see attached picture in case is not available):



Now, I would like to attach the RGMII and data_to_and_from_pins to the Zynq pins.
As far I understand, to do so I need to use the constraints, any guidance of how to do so?

EDIT

I would like to attach a device like this:

+ http://www.ti.com/tool/dp83867ergz-r-evm
+ http://www.ti.com/lit/df/snlr034/snlr034.pdf -> SCH

Into the GPIO Header in the ZynqBerry
Thanks in advance!

[Oleksandr Kiyenko]

Hello,

You just need to generate hdl wrapper for your blockdesign, then open this wrapper in editor to see exact pin names.
Create/edit constraints file. In this file you should specify GPIO pins you select with RGMII/MDIO signals on wrapper top level.

Best regards
Oleksandr Kiyenko